Guest
Is there any way of accessing the system time (not current simulation
time) in VHDL?
an example: when running a test bench, I generate a log file. I dont
want to have to manually move this log file for storage before I run
it again, so I want to put a time stamp in the name of the log file
(so the previous one doesnt get overwritten).
Would the only way to do this be to run the testbench externally (eg.
via TCL) that passes the timestamp (or other meaningful name) in as a
generic?
time) in VHDL?
an example: when running a test bench, I generate a log file. I dont
want to have to manually move this log file for storage before I run
it again, so I want to put a time stamp in the name of the log file
(so the previous one doesnt get overwritten).
Would the only way to do this be to run the testbench externally (eg.
via TCL) that passes the timestamp (or other meaningful name) in as a
generic?