Switching between the signals

J

john

Guest
Hello,

I have interfaced a CPLD to a SRAM. The SRAM has 19 bit of address bus

and 18 bit of data bus. I am using 14 bit of Address bus and 14 bit of

data bus. I am having problem implementing the following algorithm

I have to generate a 14 bit address from the CPLD and retrived the 14
bit data

After getting the data, I have to copy or replace the data with the
address bus

and then retrieve new data and send it out of the CPLD. I have to
switch between

Address and data buses. Switching between the buses is the main
problem!!

I used multiplexer but its not working for me. Please Advice me some
other techniques or

i am also attaching the code that What I did..

Thanks.
Regards
John

--Mian Sequential Machine

Begin

C0: counter port map ( counter_A_data,
equalsignalc, eq_signal,Reset_A);
CB: counter_b port map ( countb_mux_datain, DPR_CLK,
incr_B,equalsignalB,Reset_b);
CC: counter_cport map (
countc_mux_datain,equalsignalB,equalsignalc, Reset_C );
M: MUX port map (
countb_mux_datain,countc_mux_datain,equalsignalB,"00001");
M14: multiplexer port map(
sel_14bit_mux,"00000000000000",Data, Address_bus(18 downto 5)
,DPR_CLK);
L : Latch_chip port map(
Data_Bus,Data,Latch_signal, xyz,Data_out_bus(13 downto 0));

Output_Enable <= '0';
CE0 <= '0';
CE1 <= '1';
Read_write <= '1';
Latch <= sel_14bit_mux;
--Latch_signal <= not sel_14bit_mux;


Process ( State_A )

Begin

Case State_A is

When A0 =>
If ( input_signal ='1' ) Then

incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';
nextstate_A <= A1;

Else If ( input_signal ='0' ) Then
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';
nextstate_A <= A0;

End If;
End If;

When A1 =>
-- First Address get Valid --
incr_B <= '1';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';

nextstate_A <= A2;

When A2 =>
-- Data is valid on the Bus --
incr_B <= '0';
LBL <= '0';
UBL <= '0';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';

nextstate_A <= A3;

When A3 =>
-- Data becomes Address --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '1';
xyz <= '0';

nextstate_A <= A4;

When A4 =>
-- Data gets valid again --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '1';
xyz <= '0';

nextstate_A <= A5;

When A5 =>
-- Data is out --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '0';
xyz <= '1';

nextstate_A <= A6;

When A6 =>
-- Data is out --
incr_B <= '0';
LBL <= '0';
UBL <= '0';
sel_14bit_mux <= '0';
Latch_signal <= '0';
xyz <= '1';
--Data_out_bus(13 downto 0) <= Data;

nextstate_A <= A1;

When others =>

nextstate_A <= A0;
End Case;
End Process;

-- DPR Process
Process ( DPR_CLK )

Begin


If ( DPR_CLK 'event And DPR_CLK = '1') Then

State <= nextstate;
State_A <= nextstate_A;

End If;
End Process;

End DPR_ARCH;




------Latch

ntity Latch_chip is

Port (
Data_in: inout unsigned( 13 downto 0);
Data_out: out unsigned( 13 downto 0);
Select_pin: in std_logic;
Clock: in std_logic;
out_data: out unsigned ( 13 downto 0)


);

End Latch_chip;

Architecture Latch1 of Latch_chip is

Begin


Process (Data_in, Clock, Select_pin)

variable latched_value: unsigned (13 downto 0);


Begin
If ( Select_pin ='1' ) Then

latched_value := Data_in;
out_data <= Data_in;
End If;

If ( Clock ='1') Then

Data_out <= latched_value;
Else

Data_out <= NULL;

End If;

End process;

End Latch_chip;



--- MULTIPLEXER

Entity multiplexer is

Port (

Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : inout unsigned ( 13 downto 0);
Clk : in std_logic
);

End multiplexer;


Architecture muxq of multiplexer is

Begin

data_out_mux <= data_in_counter When Sel_line = '1'

Else


data_in_data_bus;

Process ( Sel_line )
Begin
End process;
End muxq;
 
Hello,

I tried to fix the Reading problem of the code. i hope that It will be
allright now! I read the literature u mentioned but could not apply it
to my problem. Where am I am misusing the hirarchery or mixing control
and data path. You are right that I designed it like connecting the
74LS00 chips on the circuit board but I do not understand whats wrong
with that! Would you please give me some simple examples or mistake in
my code so that I can fix the problem...
Thanks
john


I have interfaced a CPLD to a SRAM. The SRAM has 19 bit of address bus
and 18 bit of data bus. I am using 14 bit of Address bus and 14 bit of
data bus. I am having problem implementing the following algorithm


I have to generate a 14 bit address from the CPLD and retrived the 14
bit data, After getting the data, I have to copy or replace the data
with the address busand then retrieve new data and send it out of the
CPLD. I have to
switch between Address and data buses. Switching between the buses is
the main problem!!

I used multiplexer but its not working for me. Please Advice me some
other techniques or i am also attaching the code that What I did..

Thanks.
Regards
John


--Mian Sequential Machine


Begin


C0: counter port map ( counter_A_data,equalsignalc,
eq_signal,Reset_A);

CB: counter_b port map( countb_mux_datain, DPR_CLK,
incr_B,equalsignalB,Reset_b);

CC: counter_cport map(countc_mux_datain,equalsignalB,equalsignalc,
Reset_C );

M: MUX port map
(countb_mux_datain,countc_mux_datain,equalsignalB,"00001");

M14: multiplexer port map ( sel_14bit_mux,"00000000000000",Data,
Address_bus(18 downto 5),DPR_CLK);

L : Latch_chip port
map(Data_Bus,Data,Latch_signal,xyz,Data_out_bus(13 downto 0));


Output_Enable <= '0';
CE0 <= '0';
CE1 <= '1';
Read_write <= '1';
Latch <= sel_14bit_mux;


Process ( State_A )


Begin


Case State_A is


When A0 =>
If ( input_signal='1' ) Then

incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux<= '1';
Latch_signal <= '0';
xyz <= '0';
nextstate_A <= A1;


Else If ( input_signal ='0' ) Then
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';
nextstate_A <= A0;


End If;
End If;


When A1=>
-- First Address get Valid --
incr_B <= '1';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';

nextstate_A <= A2;


When A2 =>
-- Data is valid on the Bus --
incr_B <= '0';
LBL <= '0';
UBL <= '0';
sel_14bit_mux <= '1';
Latch_signal <= '0';
xyz <= '0';
nextstate_A <= A3;


When A3 =>
-- Data becomes Address --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '1';
xyz <= '0';

nextstate_A <= A4;


When A4 =>
-- Data gets valid again --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '1';
xyz <= '0';
nextstate_A <= A5;


When A5 =>
-- Data is out --
incr_B <= '0';
LBL <= '1';
UBL <= '1';
sel_14bit_mux <= '0';
Latch_signal <= '0';
xyz <= '1';
nextstate_A <= A6;


When A6 =>
-- Data is out --
incr_B <= '0';
LBL <= '0';
UBL <= '0';
sel_14bit_mux <= '0';
Latch_signal <= '0';
xyz <= '1';

nextstate_A <= A1;


When others =>
nextstate_A <= A0;

End Case;
End Process;


-- DPR Process
Process(DPR_CLK)

Begin

If (DPR_CLK 'event And DPR_CLK = '1') Then

State <= nextstate;
State_A <= nextstate_A;

End If;
End Process;


End DPR_ARCH;


------Latch


Entity Latch_chip is


Port (

Data_in: inout unsigned( 13 downto 0);
Data_out: out unsigned( 13 downto 0);
Select_pin:in std_logic;
Clock: in std_logic;
out_data: out unsigned ( 13 downto 0)


);

End Latch_chip;


Architecture Latch1 of Latch_chip is
Begin

Process (Data_in, Clock, Select_pin)


variable latched_value: unsigned (13 downto 0);


Begin
If ( Select_pin ='1') Then


latched_value := Data_in;
out_data <= Data_in;
End If;


If (Clock ='1') Then

Data_out <= latched_value;
Else

Data_out <= NULL;
End If;
End process;


End Latch_chip;


--- MULTIPLEXER


Entity multiplexer is


Port (


Sel_line : in std_logic;
data_in_counter : in unsigned ( 13 downto 0);
data_in_data_bus : in unsigned ( 13 downto 0);
data_out_mux : inout unsigned ( 13 downto 0);
Clk : in std_logic
);


End multiplexer;

Architecture muxq of multiplexer is

Begin

data_out_mux <= data_in_counter When Sel_line = '1' Else
data_in_data_bus;

Process (Sel_line)
Begin
End process;
End
 
john wrote:
Hello,

I tried to fix the Reading problem of the code. i hope that It will be
allright now!
Click to expand...
Don't just hope. Simulate! Check the functionality of your code by
applying stimuli and check the result against your requirements.

I read the literature u mentioned but could not apply it
to my problem.
Click to expand...
Read the part about the UART design again.

Where am I am misusing the hirarchery or mixing control
and data path. You are right that I designed it like connecting the
74LS00 chips on the circuit board but I do not understand whats wrong
with that!
Click to expand...
You're code will be hard to understand and hard to maintain. The
intention of the code is not obvious.

And if you do need a latch, a simple process will suffice. There's no
need to create a separate entity for that.

Would you please give me some simple examples or mistake in
my code so that I can fix the problem...
Click to expand...
I still think you should read
http://www.designabstraction.co.uk/Articles/Advanced%20Synthesis%20Techniques.htm
once again. The example is quite simple (UART design) yet not too
trivial to make the point. The point being: "Many HDL Designers write
RTL code at a much lower level of abstraction than is actually necessary
to achieve the desired end".

Paul.
 
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