Svar: Re: Svar: Is fixed point (ieee_proposed.fixed_pkg_c) s

  • Thread starter Svenn Are Bjerkem
  • Start date
S

Svenn Are Bjerkem

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This is what I posted on the xilinx forum http://forums.xilinx.com/t5/Synthesis/ieee-proposed-fixed-pkg-all-in-Xilinx-ISE-12-1/m-p/76151/highlight/false#M2428
I usually value comp.arch.fpga as a superior source of information.

<crosspost start>
I just want to pick up this issue for ISE 12.3 for Spartan 3A DSP.

I see differences between the ieee_proposed.fixed_pkg in $Xilinx/vhdl/src/ieee_proposed and the compatibility package for ISE 11.1 on http://www.eda-stds.org/fphdl/. I have enabled the division in the package from eda-stds.org to test if 12.3 handles the division as I want to implement a cumulative moving average algorithm which includes a division.


In both cases, ISE barfs at me with the message:

ERROR:Xst:769 - "/opt/Xilinx/12.3/ISE_DS/ISE/vhdl/src/ieee_proposed/fixed_pkg_c.vhd" line 2059: Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2


VHDL code is something like:

architecture example of some_module is

signal cma : sfixed (3 downto -9); --! signed fixed accumulator for average
signal avg_count : integer; --! Counter for number of phase measurements

begin
p_out_mux_reg : process (clk_96m) is
variable tmp : sfixed (2 downto -9); --! A temp value depending on size of phase (pi or 2pi)
begin
if rising_edge(clk_96m) then
if sel_out = '1' then
tmp := sum_pi2_sfix;
else
tmp := diff_ab2_sfix;
end if;

-- only accumulate average when value from cordic is updated.
if rdy_cordic = '1' then
cma <= resize(cma + (tmp - cma)/avg_count, cma);
avg_count <= avg_count + 1;
end if;

-- when measurement starts, initialize accumulator.
if enable_mea = '1' then
cma <= resize(tmp, cma);
avg_count <= 0;
end if;
end if;
end process;
end example;


I wonder if the Xilinx ieee_proposed is meant for VHDL-2008 or if it is useful for VHDL-93, too.

Modelsim and Rtlvision is able to make something useful out of my cma, but ISE isn't.

Since ISE barfs at the same line, independently of Xilinx code or eda-stds.org code, I guess the problem lies within ISE, but I hope I am wrong.

--
Svenn
 

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