sva

ajeetha,
i am using vcs-7.2. i am sending my code which give the error.
module top();

reg clk;
reg a,b;
initial
begin
clk =0;

a=0;
b=0;

end

always clk = #5~clk;


initial
begin
@(posedge clk);
a=0;
b=0;
@(posedge clk);@(posedge clk);
@(posedge clk);

a=1;
b=0;

@(posedge clk);@(posedge clk);
@(posedge clk);
a=0;
b=1;
@(posedge clk);@(posedge clk);
@(negedge clk);

a=0;
b=0;
$display($time,"a=%b,b=%b",a,b);

@(posedge clk);
a=0;
b=0;
@(posedge clk);@(posedge clk);
@(posedge clk);
@(posedge clk);@(posedge clk);
$finish;
end // initial begin

endmodule // top





`ifdef SVA
module try (clk,
a,
b);

input clk,a,b;

wire clk,a,b;

sequence s2;
@(posedge clk) (a || b);

endsequence

property p2;
s2;
endproperty

a2 : assert property(p2)
$display($time ," a=%b\t, b=%b\t , PROPERTY a2 IS
SUCCESSFUL \n",a,b);
else
$display($time ," a=%b\t, b=%b\t , PROPERTY a2
FAILED\n",a,b);

endmodule //
bind top try try(clk,a,b);

`endif

-------------------------------------
regards
vinay

 

[Ajeetha]

Vinay,
I don't have VCS 7.2, but I do see a problem in your code: there is
no clock for your assertion/prop p2. Instead of:

a2 : assert property(p2)

Try:

a2 : assert property(@ (posedge clk) p2)

That should help you.
Let's know.

Also, post your error that you got from vcs.

Regards
Ajeetha, CVC