sva

hi all
i am donig work in verification using system verilog.
i have written a program in sva.if i declare the clock in side the
sequence then simulator give the syntax error.if i declare clock inside
property then it work.i am using vcs for simulation.
regards
vinay

 

[Ajeetha]

Vinay,
Show us a sample piece of code that gives you syntax error. VCS
does allow clock inside sequence. Which VCS version do you use?

Ajeetha, CVC