(SVA) Use bind to infer all the signals within a module?

[Shenli]

Hi all,

We know that SystemVerilog Assertion can be used in two way: 1.
embedded 2. bind to a dedicated property module.

But when use bind, people always input the interface, so we just infer
the signals on the module interface.

So can we use bind to infer all the signals within a module
theoretically?

Best regards,
Shenli

 

[Jonathan Bromley]

On 29 Dec 2006 19:07:20 -0800, "Shenli" <zhushenli@gmail.com> wrote:

Hi all,

We know that SystemVerilog Assertion can be used in two way: 1.
embedded 2. bind to a dedicated property module.

And also, of course, create a module with assertions, and
instantiate that in the usual way. It's not essential to use
'bind' to instantiate assertion modules.

But when use bind, people always input the interface, so we just infer
the signals on the module interface.

I'm not sure I understand... do you mean that the assertion
module sees only those signals that are connected to its ports
by the bind instantiation?

So can we use bind to infer all the signals within a module
theoretically?

(.*) in the port connection list? The LRM clearly states
this should be possible. I'm not sure if tools yet support it.

Why would you want to do this? If you want to inspect
*all* the internal structure of a module, the assertions
you write will never be re-usable and it's pointless to
bind them into the target module.

============= (off topic rant) ===========

There is a very interesting theoretical point here. SystemVerilog
is not generally thought of as an "aspect-oriented" language
in the sense that 'e' is. Let's ignore, for now, the arguments
about whether 'e' is truly aspect-oriented, and whether AO
is a good idea.

Anyway, 'e' has the special property that it
allows you to extend existing module and class definitions
without using inheritance.

Now for the bomshell: SystemVerilog has module extension
too. 'bind' is, precisely, the extension of an existing module
definition by adding a new module instance to it. If we
can 'bind' a module instance, surely we can also 'bind'
a continuous assign statement, or an always block,
or a declaration... in other words, "bind" works much
like "extend" in 'e', except that today it's limited to
adding instantiations to its target.

Just a thought.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Shenli]

Jonathan Bromley wrote:

On 29 Dec 2006 19:07:20 -0800, "Shenli" <zhushenli@gmail.com> wrote:

Hi all,

We know that SystemVerilog Assertion can be used in two way: 1.
embedded 2. bind to a dedicated property module.

And also, of course, create a module with assertions, and
instantiate that in the usual way. It's not essential to use
'bind' to instantiate assertion modules.

But when use bind, people always input the interface, so we just infer
the signals on the module interface.

I'm not sure I understand... do you mean that the assertion
module sees only those signals that are connected to its ports
by the bind instantiation?

[snip]

Hi Jonathan,

Thanks a lot!
I think you are correct!

Do you mean (.*) includes all the signals (both on the port and
internal)?

I have concluded your idea, is it correct?
1. Use embeded assertion to inspect *all* the internal signal of a
module.
2. Use "bind" to inspect signals on the ports/interface if we want to
reuse it.

Best regards,
Shenli

So can we use bind to infer all the signals within a module
theoretically?

(.*) in the port connection list? The LRM clearly states
this should be possible. I'm not sure if tools yet support it.

Why would you want to do this? If you want to inspect
*all* the internal structure of a module, the assertions
you write will never be re-usable and it's pointless to
bind them into the target module.

============= (off topic rant) ===========

There is a very interesting theoretical point here. SystemVerilog
is not generally thought of as an "aspect-oriented" language
in the sense that 'e' is. Let's ignore, for now, the arguments
about whether 'e' is truly aspect-oriented, and whether AO
is a good idea.

Anyway, 'e' has the special property that it
allows you to extend existing module and class definitions
without using inheritance.

Now for the bomshell: SystemVerilog has module extension
too. 'bind' is, precisely, the extension of an existing module
definition by adding a new module instance to it. If we
can 'bind' a module instance, surely we can also 'bind'
a continuous assign statement, or an always block,
or a declaration... in other words, "bind" works much
like "extend" in 'e', except that today it's limited to
adding instantiations to its target.

Just a thought.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On 30 Dec 2006 16:54:41 -0800, "Shenli" <zhushenli@gmail.com> wrote:

Do you mean (.*) includes all the signals (both on the port and
internal)?

No. It has the usual meaning: every port on the module is
connected to a signal with the same name as the port.
In this context, the neat thing about .* is that you can add
more signals to the port list of the module, and the same
"bind" statement will continue to work without change.

I have concluded your idea, is it correct?
1. Use embeded assertion to inspect *all* the internal signal of a
module.
2. Use "bind" to inspect signals on the ports/interface if we want to
reuse it.

That would be my choice, yes.

For standard interconnect (AHB bus, etc) I would probably try
to build a SystemVerilog interface to describe the bus, and
include some assertions within that interface. Then, I get
my assertions automatically wherever I use the bus.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.