SVA synthesis

C

CS student

Guest
Hi,
I'm interested in synthesis of System Verilog Assertions (and also the
synthesis of coverage , e.g., 'covergroup' if possible)
Can you please direct me to articles etc.. that deal with it?
Thanks a lot
 
"CS student" <israelaix@hotmail.com> wrote in message
news:1177596676.555139.200400@t38g2000prd.googlegroups.com...
Hi,
I'm interested in synthesis of System Verilog Assertions (and also the
synthesis of coverage , e.g., 'covergroup' if possible)
Can you please direct me to articles etc.. that deal with it?
Thanks a lot
Click to expand...
Have a look at Dialite from Temento, they can translate SVA/PSL into
hardware monitors,

http://www.temento.com/solutions/fpga.php?idpage=100

Hans.
www.ht-lab.com


>
 
On Apr 27, 11:09 am, "HT-Lab" <han...@ht-lab.com> wrote:
"CS student" <israel...@hotmail.com> wrote in message

news:1177596676.555139.200400@t38g2000prd.googlegroups.com...

Hi,
I'm interested in synthesis of System Verilog Assertions (and also the
synthesis of coverage , e.g., 'covergroup' if possible)
Can you please direct me to articles etc.. that deal with it?
Thanks a lot

Have a look at Dialite from Temento, they can translate SVA/PSL into
hardware monitors,

http://www.temento.com/solutions/fpga.php?idpage=100

Hans.www.ht-lab.com
Click to expand...
Hi Hans,
I'm interested in synthesizing SVA in sake of emulation etc...
I know there exist current methods for synthesizing assertions such as
PSL, but, i'm interested in synthesizing SVA that contain the coverage
statments, such as the 'cover' property (this may be harder than
regular assertions, since it may involve memory allocation for keeping
the coverage results).

Thanks a lot
 
"CS student" <israelaix@hotmail.com> wrote in message
news:1177669762.226267.243160@o40g2000prh.googlegroups.com...
On Apr 27, 11:09 am, "HT-Lab" <han...@ht-lab.com> wrote:
"CS student" <israel...@hotmail.com> wrote in message

news:1177596676.555139.200400@t38g2000prd.googlegroups.com...

Hi,
I'm interested in synthesis of System Verilog Assertions (and also the
synthesis of coverage , e.g., 'covergroup' if possible)
Can you please direct me to articles etc.. that deal with it?
Thanks a lot

Have a look at Dialite from Temento, they can translate SVA/PSL into
hardware monitors,

http://www.temento.com/solutions/fpga.php?idpage=100

Hans.www.ht-lab.com

Hi Hans,
I'm interested in synthesizing SVA in sake of emulation etc...
I know there exist current methods for synthesizing assertions such as
PSL, but, i'm interested in synthesizing SVA that contain the coverage
statments, such as the 'cover' property (this may be harder than
regular assertions, since it may involve memory allocation for keeping
the coverage results).

Thanks a lot
Click to expand...
The cover statement is also supported, it simply counts the number of
passes. You can also connect the output of the SVA monitor to a history
register which then records signals during the assertion failure.

Hans
www.ht-lab.com


>
 
On Apr 27, 2:16 pm, "HT-Lab" <han...@ht-lab.com> wrote:
"CS student" <israel...@hotmail.com> wrote in message

news:1177669762.226267.243160@o40g2000prh.googlegroups.com...





On Apr 27, 11:09 am, "HT-Lab" <han...@ht-lab.com> wrote:
"CS student" <israel...@hotmail.com> wrote in message

news:1177596676.555139.200400@t38g2000prd.googlegroups.com...

Hi,
I'm interested in synthesis of System Verilog Assertions (and also the
synthesis of coverage , e.g., 'covergroup' if possible)
Can you please direct me to articles etc.. that deal with it?
Thanks a lot

Have a look at Dialite from Temento, they can translate SVA/PSL into
hardware monitors,

http://www.temento.com/solutions/fpga.php?idpage=100

Hans.www.ht-lab.com

Hi Hans,
I'm interested in synthesizing SVA in sake of emulation etc...
I know there exist current methods for synthesizing assertions such as
PSL, but, i'm interested in synthesizing SVA that contain the coverage
statments, such as the 'cover' property (this may be harder than
regular assertions, since it may involve memory allocation for keeping
the coverage results).

Thanks a lot

The cover statement is also supported, it simply counts the number of
passes. You can also connect the output of the SVA monitor to a history
register which then records signals during the assertion failure.

Hanswww.ht-lab.com
Click to expand...
Thanks Hans,
I've looked at the URL you told me.
I'm interested in more general algorithm for synthesizing SVA,
regardless of a specific emulator that an EDA provides.
Such an algorithm can be combined with a desired emulator when needed.
Thus, i will be glad if you could direct me to an article that deals
with the synthesis of SVA (assert + cover) algorithm itself.
I know there are articles that describe the synthesis of PSL
statements, but these are assertions rathere than coverage monitors.
Thanks a lot
 
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