Guest
I am new to SVAs. I am trying to detect when a signal is a pulse (i.e.
either asserted or de-asserted for just one clock cycle). The signal
can change state, but I want it to remain in the state for at least 2
clock cycles. I may want to change this to at least n clock cycles
once I have the asertion working correctly. Below is the construct I
am using.
assert_packet_mem_afull_0_not_a_pulse:
assert property (@(posedge clk) disable iff(!reset_n) (!
packet_mem_afull_0_temp [*2:$] ##1 packet_mem_afull_0_temp [*2:$] ##1 !
packet_mem_afull_0_temp [*2:$]))
else $error ("ERROR: packet_mem_afull_0 was a pulse");
The signal I am monitoring is packet_mem_afull_0_temp. I am forcing
the signal to violate this assertion by de-asserting it for one clock
cycle when it is asserted and by asserting it for one clock cycle when
it is de-asserted. The stimulus is as follows: the signal powers up de-
asserted. It remains de-asserted for approximately 12,000 clock
cycles, then it asserts for 5 clock cycles, it de-asserts for one
clock cycle, then it asserts for 20 clock cycles, then it de-asserts
for 5 clock cycles, then it asserts for one clock cycle, then it de-
asserts for the rest of the simulation.
The assertion fires at the end of every cycle that the signal is
asserted and also one cycle after the signal is asserted for the final
time. The assertion does not fire at the end of cycles when the signal
is deasserted.
Any help would be greatly appreciated.
Brian
either asserted or de-asserted for just one clock cycle). The signal
can change state, but I want it to remain in the state for at least 2
clock cycles. I may want to change this to at least n clock cycles
once I have the asertion working correctly. Below is the construct I
am using.
assert_packet_mem_afull_0_not_a_pulse:
assert property (@(posedge clk) disable iff(!reset_n) (!
packet_mem_afull_0_temp [*2:$] ##1 packet_mem_afull_0_temp [*2:$] ##1 !
packet_mem_afull_0_temp [*2:$]))
else $error ("ERROR: packet_mem_afull_0 was a pulse");
The signal I am monitoring is packet_mem_afull_0_temp. I am forcing
the signal to violate this assertion by de-asserting it for one clock
cycle when it is asserted and by asserting it for one clock cycle when
it is de-asserted. The stimulus is as follows: the signal powers up de-
asserted. It remains de-asserted for approximately 12,000 clock
cycles, then it asserts for 5 clock cycles, it de-asserts for one
clock cycle, then it asserts for 20 clock cycles, then it de-asserts
for 5 clock cycles, then it asserts for one clock cycle, then it de-
asserts for the rest of the simulation.
The assertion fires at the end of every cycle that the signal is
asserted and also one cycle after the signal is asserted for the final
time. The assertion does not fire at the end of cycles when the signal
is deasserted.
Any help would be greatly appreciated.
Brian
