P
Paul Richardson
Guest
I am new to the world of assertions, I am tryinng to do the following
sequence/property/assertion which does the following:
I have a bus that is driven to a particular value, if a different bus,
2 cycles later does not assume
the same value, I want to assert that fact , I am trying to figure out
how to construct the sequence/property/assertion code such that I wait
for a value (or at least a non zero value), and if I do not
see that value the sequence/property/assertion combination does not
fire. This a clock based design,
I suppose I could write verilog to do the test for the inital value and
then use sequence/properties
within that verilog to fire an assertion as I described above.
This running under VCS 7.2 with sva switched on, any tips will be much
appreciated
/pgr
sequence/property/assertion which does the following:
I have a bus that is driven to a particular value, if a different bus,
2 cycles later does not assume
the same value, I want to assert that fact , I am trying to figure out
how to construct the sequence/property/assertion code such that I wait
for a value (or at least a non zero value), and if I do not
see that value the sequence/property/assertion combination does not
fire. This a clock based design,
I suppose I could write verilog to do the test for the inital value and
then use sequence/properties
within that verilog to fire an assertion as I described above.
This running under VCS 7.2 with sva switched on, any tips will be much
appreciated
/pgr