SV+virtual interface+port connections

Hi,

This is what I wish to do:

I have modules A and B connected inside of
module TB through common Verilog module ports.
I want to monitor the signals between A and B
and place the monitoring code in a class
method. My understanding is, that I need
a virtual interface in the class that will
be connected to an actual interface.

The problem is that I don't have
an interface between module A and B and I
wouldn't want to change anything regarding
modules A and B.

Can I instantiate an interface and make the
signals in the interface equivalent to the
signals between A and B, or at least driven by
the signals between A and B.

Any suggestions?

Regards,
e

 

[Jonathan Bromley]

On Mon, 27 Aug 2007 05:36:09 -0700, eascheiber@yahoo.com wrote:

This is what I wish to do:

[snip]

Can I instantiate an interface and make the
signals in the interface equivalent to the
signals between A and B, or at least driven by
the signals between A and B.

Yup. Try this:

module A(input a); ... endmodule

module B(output b); ... endmodule

interface I();
logic L;
modport for_testbench(inout L);
endinterface : I

module TB;
I inst_I();
A inst_A(.a(inst_I.L);
B inst_B(.b(inst_I.L);
endmodule : TB

Now you can take a virtual interface reference to
TB.inst_I.for_testbench, and you can see the
interconnecting signal L through that modport.

Alternatively, if your top-leve TB already exists, you
could create the interface and alias its contents on to
the interconnect. The VMM book suggests this approach.
I confess that I find it unnecessarily cumbersome.
--
Jonathan Bromley, Consultant

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