SV transaction sequence dependency constraint?

[Shenli]

Hi all,

Is there any good methods to write SystemVerilog transaction sequence
dependency constraint?

For example, in below SV code, I want to always generate IDLE
transaction after WRITE (i.e. WRITE after WRITE or READ after WRITE is
illegal).

//--- SV code start---
//define transactions
typedef enum { WRITE=1,READ=2,IDLE=4} cmd_t;
class Packet;
...
rand cmd_t cmd;
...
endclass
Packet p;
initial begin
p = new();
p.randomize();
end
//--- SV code end---

Best regards,
Davy