SV: Port connection rules for interfaces!

[Ravi S Gowda]

SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi

 

[Srinivasan Venkataramanan]

Hi Ravi,
Yes you are correct in interperting the LRM and so is VCS But
this is an elaboration time check and if in case you just want to compile
your SV code, use vlogan. i.e. use:

vlogan -sverilog file.sv

NOTE: This command shall work only in VCS-MX AFAIK. If you need it with pure
VCS, send a support email to vcs_support@...
Regards,
Srinivasan
--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1105351042.884894.294480@c13g2000cwb.googlegroups.com...

SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi