SV: Port connection rules for interfaces!

[Ravi S Gowda]

SystemVerilog LRM says
"An interface port can not be left unconnected"
Accordingly in VCS the following code won't compile

interface inf;
logic l0;
endinterface

module m(inf i);

endmodule

//module top();
// inf i();
// m m0(i);
//endmodule

If the commented out portion above is included, SV gets satisfied.

So it means.. If I write a piece of SV... I should also be
ready with a top to compile it!.
Right? Wrong? Any other work around if I am just trying to see
the compilability of the above piece of code?

-Ravi