SV logic/wire question

This question is for SV LRM gurus. I often declare my modules as follows:

`default_net_type none
module m...
(
input wire ...
inout wire ...
output logic
);

logic ...

endmodule : m
`default_net_type wire

I use "`default_net_type none" at the beginning to catch nets not declared at simulation time. I also switched from wire/reg for I/Os and signals to logic for all. The side-effect of "`default_net_type none" seems to be force me to declare module inputs and inouts as wires!

I am not sure why that does not affect outputs.

Is there a better solution to catch undeclared nets and at the same time declare all signals (I/Os or otherwise) as logic?

-- Amal

 

[Mark Curry]

In article <e287d218-36e9-404c-b80b-9656b7b424ab@googlegroups.com>,
<amal.khailtash@gmail.com> wrote:

This question is for SV LRM gurus. I often declare my modules as follows:

`default_net_type none
module m...
(
input wire ...
inout wire ...
output logic
);

logic ...

endmodule : m
`default_net_type wire

I use "`default_net_type none" at the beginning to catch nets not declared at
simulation time. I also switched from wire/reg for I/Os and signals to logic
for all. The side-effect of "`default_net_type none" seems to be force me to
declare module inputs and inouts as wires!

I am not sure why that does not affect outputs.

Is there a better solution to catch undeclared nets and at the same time
declare all signals (I/Os or otherwise) as logic?

I'm unsure what you're question is. Inputs and inouts must have a net type.
This has always been the case for verilog. When you turned off
the default_net_type of wire, then yes, you must explicitly
declare the input (or inout) as a wire.

I use this trick in all my code to catch undeclared nets - i.e. set
'default_net_type none at the top of my file, and return
it to 'default_net_type wire at the bottom ( so I don't clobber code
from my coworkers who don't like to do this ).

Cliff had issues with this back in the day, implying that this trick could
lead to real code errors. I don't believe it, and the assertion's never
been backed up. He suggested some alternative to the SV folks - I don't
rememeber details, and whether or not it was picked up.

In any event your style works fine, and is used often.

Regards,

Mark

 

On Tuesday, October 22, 2013 3:23:01 PM UTC-4, Mark Curry wrote:

In article <e287d218-36e9-404c-b80b-9656b7b424ab@googlegroups.com>,

amal.khailtash@gmail.com> wrote:

This question is for SV LRM gurus. I often declare my modules as follows:



`default_net_type none

module m...

(

input wire ...

inout wire ...

output logic

);



logic ...



endmodule : m

`default_net_type wire



I use "`default_net_type none" at the beginning to catch nets not declared at

simulation time. I also switched from wire/reg for I/Os and signals to logic

for all. The side-effect of "`default_net_type none" seems to be force me to

declare module inputs and inouts as wires!



I am not sure why that does not affect outputs.



Is there a better solution to catch undeclared nets and at the same time

declare all signals (I/Os or otherwise) as logic?



I'm unsure what you're question is. Inputs and inouts must have a net type.

This has always been the case for verilog. When you turned off

the default_net_type of wire, then yes, you must explicitly

declare the input (or inout) as a wire.



I use this trick in all my code to catch undeclared nets - i.e. set

'default_net_type none at the top of my file, and return

it to 'default_net_type wire at the bottom ( so I don't clobber code

from my coworkers who don't like to do this ).



Cliff had issues with this back in the day, implying that this trick could

lead to real code errors. I don't believe it, and the assertion's never

been backed up. He suggested some alternative to the SV folks - I don't

rememeber details, and whether or not it was picked up.



In any event your style works fine, and is used often.



Regards,



Mark

That was my exact intention for using "`default_net_type none" to catch undeclared nets. I like the strong type checking of VHDL and the reason I moved to using logic was to catch multiple drivers on wire declarations that seem to go through some tools as warnings. These two alone catch many mistakes by different coders and groups.

My specific question was why the same argument is not true for output ports? When I have "`default_net_type none", doesn't it apply to outputs as well as inputs and inouts?

In this case, "output logic ..." seems to be fine and I do not need to declare its net type (wire/reg)? I may not have read LRM properly and my VHDL experience does not seem to help on that front.

-- Amal

 

[Mark Curry]

In article <44c882d5-3986-4eb5-9764-9c81d87427a9@googlegroups.com>,
<amal.khailtash@gmail.com> wrote:

<snip>

That was my exact intention for using "`default_net_type none" to catch
undeclared nets. I like the strong type checking of VHDL and the reason
I moved to using logic was to catch multiple drivers on wire declarations
that seem to go through some tools as warnings. These two alone catch
many mistakes by different coders and groups.

My specific question was why the same argument is not true for output ports?
When I have "`default_net_type none", doesn't it apply to outputs as well as
inputs and inouts?

In this case, "output logic ..." seems to be fine and I do not need to
declare its net type (wire/reg)? I may not have read LRM properly and my
VHDL experience does not seem to help on that front.

"Logic" is the same in every was as "reg". You can use either/or freely in
Systemverilog. They are exactly the same. I don't use "logic" at all, I use
"reg", as I've used it too long to change for no reason.

The history of these two is a little convoluted, but it is what it is.
"logic" is a valid type.

Inputs and outputs (and inouts) are treated the same with regard
to the default_net_type. There's just restrictions on what types
can be used for each kind of port.

So you can declare:
`default_net_type none
module foo
(
input wire clk_i, // legal - input is a net type
input reg reset_i, // illegal, input is not a net type
input logic enable_i, // illegal, same as above.
input d_i, // illegal - undeclared type
inout wire bus_io, // legal, inout is a net type
inout logic bus2_io, // illegal - inout is NOT a net type
inout reg bus3_io, // illegal - same as above
output wire q_o, // legal
output reg y_o, // legal output may be of net or variable type
output logic z_o, // legal same as above
output m_o // illegal - undeclared type
);

Regards,

Mark

 

[Mike Redfire]

On Wednesday, October 23, 2013 7:18:01 PM UTC+4, Mark Curry wrote:

"Logic" is the same in every was as "reg". You can use either/or freely in

Systemverilog. They are exactly the same. I don't use "logic" at all, I use

"reg", as I've used it too long to change for no reason.

Well, as I know, "logic" is not "reg". "Logic" be a "wire" or a "reg", for example:

logic abc;
assign abc = 1'b0; // Legal

-------------

logic abc;
always @( posed clk) abc <= abc + 1; // Legal

-------------

But:

wire abc;
always @( posed clk) abc <= abc + 1; // Illegal

-------------

reg abc;
assign abc = 1'b0; // Illegal