[SV] Interfaces should be compiled or included?

[Andy Luotto]

I have written a verilog interface with its methods and clocking block
(and a couple of typedefs) in a file xxx_if.sv, which is supposed to
be used by different verlog modules (or files: I put one module in
each file)
should I compile the xxx_if.v or should I include the xxx_if.v in
every file which uses it?
should I put it into a package (system verilog can support packages)
what about classes?
please advice about SW engineering using system verilog: the language
now seems to allow much better code management

regards

 

[Jonathan Bromley]

On Tue, 8 Apr 2008 08:57:13 -0700 (PDT), Andy Luotto wrote:

I have written a verilog interface with its methods and clocking block
(and a couple of typedefs) in a file xxx_if.sv, which is supposed to
be used by different verlog modules (or files: I put one module in
each file)
should I compile the xxx_if.v or should I include the xxx_if.v in
every file which uses it?
should I put it into a package (system verilog can support packages)
what about classes?

If you're using a virtual interface to connect things to an
interface instance, you need two things: (1) the definition of
the interface itself, so you can instantiate it; (2) the declaration
of the virtual interface data type, so that you can create variables
of that type.

The interface itself is a design unit and can be compiled separately;
it cannot go in a package.

You could create a package with a typedef in it for the virtual,
but there's probably no point in doing that separately. I usually
put the virtual interface typedef in the same package that contains
definitions of the classes that will link to it; then the package
and the interface can all go in one file, capturing the whole of
the link between my testbench and the wiring.

interface My_TB_Intf(input bit clk);
wire W; //etc
clocking TB_CB @(posedge clk); inout W; endclocking
modport TB_MP(clocking TB_CB);
endinterface

package My_TB_BFM;

typedef virtual My_TB_Intf.TB_MP My_TB_VI;

class My_BFM;
My_TB_VI intf_hook;
function new(My_TB_VI hook);
intf_hook = hook;
endfunction : new
task drive(bit B);
@(intf_hook.TB_CB);
intf_hook.TB_CB.W <= B;
endfunction
endclass

endpackage

please advice about SW engineering using system verilog: the language
now seems to allow much better code management

It does indeed - packages are a Good Thing (TM). From my very
practical point of view, "SW engineering" is all about:
- keeping together those things that belong together
- keeping separate those things that should be separate
- knowing which is which

But the theorists will probably try to tell you a whole lot
more stuff about that
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.