SV interface in modules instantiated inside a generate state

F

fpgabuilder

Guest
How do I replace the i/os on the modules repeatedly instantiated as
below with an instance of an interface?

module top_level
#(parameter
NUM_OF_ADC_INTERFACES=`ADC_BRD_FPGA_NUM_OF_ADC_INTERFACES,

NUM_OF_CHANNELS_PER_ADC_INTERFACE=`ADC_BRD_FPGA_NUM_OF_CHANNELS_PER_ADC_INTERFACE
)
(
//adc channel interfaces
input [NUM_OF_ADC_INTERFACES-1:0] dco_p,
input [NUM_OF_ADC_INTERFACES-1:0] dco_n,
input [NUM_OF_ADC_INTERFACES-1:0] fr_p,
input [NUM_OF_ADC_INTERFACES-1:0] fr_n,
input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dA_p,
input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dA_n,
input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dB_p,
input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dB_n
);


//deserializer
genvar i;
generate for
(i=0;i<NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE;i=i+1)
begin : adc_in
deserializer deserializer
(
//adc if pins
.dco_p(dco_p[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
.dco_n(dco_n[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
.fr_p(fr_p[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
.fr_n(fr_n[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
.dA_p(dA_p),
.dA_n(dA_n),
.dB_p(dB_p),
.dB_n(dB_n),

//parallel data
.dout(dout),
.pclk(pclk)
);
end
endgenerate


I am confused about how I can use one interface block that represents
a bundle of bundle of wires at the top-level and then connect to the
same interface block at a lower-level where one instance of module
within a generate statement gets only one bundle of wires from the
entire bundle. E.g. -

module adc_brd_fpga
#(parameter
NUM_OF_ADC_INTERFACES=`ADC_BRD_FPGA_NUM_OF_ADC_INTERFACES,

NUM_OF_CHANNELS_PER_ADC_INTERFACE=`ADC_BRD_FPGA_NUM_OF_CHANNELS_PER_ADC_INTERFACE
)
(
//adc channel interfaces
adc_if.adcFpgaRx (*) //modport adcFpgaRx contains a generate
statement for
//all the channels.
);

//deserializer
genvar i;
generate for
(i=0;i<NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE;i=i+1)
begin : adc_in
deserializer deserializer
(
//adc if pins
adc_if.channelRx(*),

//parallel data
deser_if.tx(*)
);
end
endgenerate

endmodule


TIA,
Sanjay
 
On Mar 3, 12:37 pm, fpgabuilder <parekh...@gmail.com> wrote:
How do I replace the i/os on the modules repeatedly instantiated as
below with an instance of an interface?

module top_level
  #(parameter
    NUM_OF_ADC_INTERFACES=`ADC_BRD_FPGA_NUM_OF_ADC_INTERFACES,

NUM_OF_CHANNELS_PER_ADC_INTERFACE=`ADC_BRD_FPGA_NUM_OF_CHANNELS_PER_ADC_INTERFACE
   )
   (
    //adc channel interfaces
    input [NUM_OF_ADC_INTERFACES-1:0] dco_p,
    input [NUM_OF_ADC_INTERFACES-1:0] dco_n,
    input [NUM_OF_ADC_INTERFACES-1:0] fr_p,
    input [NUM_OF_ADC_INTERFACES-1:0] fr_n,
    input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dA_p,
    input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dA_n,
    input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dB_p,
    input
[NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE-1:0] dB_n
   );

  //deserializer
  genvar i;
  generate for
(i=0;i<NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE;i=i+1)
    begin : adc_in
      deserializer deserializer
      (
        //adc if pins
        .dco_p(dco_p[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
        .dco_n(dco_n[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
        .fr_p(fr_p[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
        .fr_n(fr_n[i/NUM_OF_CHANNELS_PER_ADC_INTERFACE]),
        .dA_p(dA_p),
        .dA_n(dA_n),
        .dB_p(dB_p),
        .dB_n(dB_n),

        //parallel data
        .dout(dout),
        .pclk(pclk)
      );
    end
  endgenerate

I am confused about how I can use one interface block that represents
a bundle of bundle of wires at the top-level and then connect to the
same interface block at a lower-level where one instance of module
within a generate statement gets only one bundle of wires from the
entire bundle.  E.g. -

module adc_brd_fpga
  #(parameter
    NUM_OF_ADC_INTERFACES=`ADC_BRD_FPGA_NUM_OF_ADC_INTERFACES,

NUM_OF_CHANNELS_PER_ADC_INTERFACE=`ADC_BRD_FPGA_NUM_OF_CHANNELS_PER_ADC_INTERFACE
   )
   (
    //adc channel interfaces
      adc_if.adcFpgaRx (*) //modport adcFpgaRx contains a generate
statement for
                           //all the channels..
   );

  //deserializer
  genvar i;
  generate for
(i=0;i<NUM_OF_ADC_INTERFACES*NUM_OF_CHANNELS_PER_ADC_INTERFACE;i=i+1)
    begin : adc_in
      deserializer deserializer
      (
        //adc if pins
        adc_if.channelRx(*),

        //parallel data
        deser_if.tx(*)
      );
    end
  endgenerate

endmodule

TIA,
Sanjay
Click to expand...

Looking around a bit, I found these two papers that provides a good
insight into the SV Interfaces. I note them here for the benefit of
others in the same boat...

http://www.doulos.com/downloads/events/DVCon07_Doulos_SysVlog_presentation.pdf
- Good overview of the interface blocks.

Another good reference is http://www.syosil.com/files/publications/FDL04_jensen_kruse_ecker_zambaldi.pdf.
Besides other things, this paper talks about horizontal and vertical
interface topologies and how currently vertical implementation is a
problem especially in synthesis.
 
On 2010-03-03 17:00:26 -0800, fpgabuilder said:
Looking around a bit, I found these two papers that provides a good
insight into the SV Interfaces. I note them here for the benefit of
others in the same boat...

http://www.doulos.com/downloads/events/DVCon07_Doulos_SysVlog_presentation.pdf
- Good overview of the interface blocks.
Click to expand...
Thanks for the link! I've run into this exact issue with APB/AHB buses
to multiple slaves. It would be nice to use this idea. However, as
Jonanthan points out SEVERAL TIMES, this isn't supported in any tools.

Jonathan, you wrote this three years ago, which was the stone age for
SV. Any news on which, if any tools support this now? Synopsys
VCS/DC/Certify??? I can wish...

Thanks,

David
 
On Thu, 4 Mar 2010 10:48:09 -0800, David Rogoff wrote:

Jonathan, you wrote this three years ago, which was the stone age for
SV.
Click to expand...
We're now in the Dark Ages, when marauding tribes can
single-handedly destroy entire nascent civilizations...

Any news on which, if any tools support this now? Synopsys
VCS/DC/Certify??? I can wish...
Click to expand...
You can wish all you like, but it probably won't do you
a great deal of good. At the last count I found exactly
one simulator, and no synthesis tools, supporting modport
expressions. Modports inside generates still seem to be
a good way to get mystery compiler crashes or "not yet
implemented" diagnostics. I have been pushing for years
to try to get SV interfaces sorted out properly, with
essentially no success - user interest is limited, and
the tool developer community is much more worried about
other big issues in SV language development.

The result is that I (speaking purely personally) am
pretty much ready to throw in the towel on interfaces
for RTL design. I'm beginning to suspect that the
future lies not there, but with really sophisticated
code generator mechanisms along the lines of MyHDL.

Ho hum.
--
Jonathan Bromley
 
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