SV: interface, class, module qn

[Ravi S Gowda]

Can some body let me know which of the following statements
is NOT true about SystemVerilog (for all items prefix "for whatever
reason" )

1) interface can be instantiated inside a class
2) class can be instantiated and newed inside an interface
3) class can be instantiated inside a module and be newed
4) module can be instantiated inside a class!
-ravi

 

[Swapnajit Mittra]

Ravi S Gowda wrote:

Can some body let me know which of the following statements
is NOT true about SystemVerilog (for all items prefix "for whatever
reason" )

1) interface can be instantiated inside a class
2) class can be instantiated and newed inside an interface
3) class can be instantiated inside a module and be newed
4) module can be instantiated inside a class!
-ravi

In stead of giving you 'yes' or 'no' answers, which will not
help you to understand the reasons behind the answers, let us
consider these:

o A class is a variable type, similar to, say, a reg
o An interface is an entity, similar to a module.

Now, go back and check the validity of 1-4 above replacing
'interface' by 'module' and 'class' by 'reg'.

More on interface:
http://www.project-veripage.com/interface_1.php

More on class:
http://www.project-veripage.com/sv_class_1.php

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[Ravi S Gowda]

Swapnajit,
Thanks for the answer. So it makes 1) and 4) FALSE.
I understand it mostly now, except that I am little lost
on 1) as the SV LRM has the following example for
virtual interfaces. In this example it seems that an interface
could indeed be called inside a class. Can you shed some
light on this? Pardon me if there is something trivial that I am
missing here.
-ravi

interface SBus; // A Simple bus interface
logic req, grant;
logic [7:0] addr, data;
endinterface
class SBusTransctor; // SBus transactor class
virtual SBus bus; // virtual interface of type Sbus
function new( virtual SBus s );
bus = s; // initialize the virtual interface
endfunction
task request(); // request the bus
bus.req <= 1'b1;
endtask
task wait_for_bus(); // wait for the bus to be granted
@(posedge bus.grant);
endtask
endclass

 

[Srinivasan Venkataramanan]

Hi Ravi,
What you are referring to is "virtual interface" and is a nice
feature of SV, IMHO. Yes, it does allow interfaces to be referred to by
dynamic object such as class, but the "instance" of the virtual interface
has to be a static one. i.e. you need to initialize the virtual interface to
a known static instance.

The example in LRM 19.8 shows that clearly.

HTH,
Sri

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned
"Ravi S Gowda" <kanakaravi@gmail.com> wrote in message
news:1110784557.996301.180200@z14g2000cwz.googlegroups.com...

Swapnajit,
Thanks for the answer. So it makes 1) and 4) FALSE.
I understand it mostly now, except that I am little lost
on 1) as the SV LRM has the following example for
virtual interfaces. In this example it seems that an interface
could indeed be called inside a class. Can you shed some
light on this? Pardon me if there is something trivial that I am
missing here.
-ravi

interface SBus; // A Simple bus interface
logic req, grant;
logic [7:0] addr, data;
endinterface
class SBusTransctor; // SBus transactor class
virtual SBus bus; // virtual interface of type Sbus
function new( virtual SBus s );
bus = s; // initialize the virtual interface
endfunction
task request(); // request the bus
bus.req <= 1'b1;
endtask
task wait_for_bus(); // wait for the bus to be granted
@(posedge bus.grant);
endtask
endclass