supply sensitive interface elements

[Erik Wanta]

I want to use supply sensitive interface elements. For verilog-AMS, I
add the following syntax to the code to make it supply sensitive.
What if I want to simulate both RTL and verilog-AMS code and still use
supply sensitive interface elements? That is, is there a way to use
the supply sensitive syntax in the RTL code and have it be used when
running AMS Designer and ignored if I am just running nc-verilog?

// define pin sensitivities
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d0;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) sl;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d1;
output (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) x;

// supply declarations for supply sensitivity
electrical (* integer inh_conn_prop_name="vdd" ;
integer inh_conn_def_value="cds_globals.\vdd! "; *)
\vdd! ;
electrical (* integer inh_conn_prop_name="vss" ;
integer inh_conn_def_value="cds_globals.\vss! "; *)
\vss! ;

---
Erik

 

[Han Speek]

Erik Wanta wrote:

I want to use supply sensitive interface elements. For verilog-AMS, I
add the following syntax to the code to make it supply sensitive.
What if I want to simulate both RTL and verilog-AMS code and still use
supply sensitive interface elements? That is, is there a way to use
the supply sensitive syntax in the RTL code and have it be used when
running AMS Designer and ignored if I am just running nc-verilog?

// define pin sensitivities
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d0;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) sl;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d1;
output (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) x;

// supply declarations for supply sensitivity
electrical (* integer inh_conn_prop_name="vdd" ;
integer inh_conn_def_value="cds_globals.\vdd! "; *)
\vdd! ;
electrical (* integer inh_conn_prop_name="vss" ;
integer inh_conn_def_value="cds_globals.\vss! "; *)
\vss! ;

---
Erik

Hi Erik,

You can include the parts you don't want nc-verilog to see in pairs of
`ifdef INCA
....
`endif
conditionals.
However, don't forget to check the "Conditionally include language
extensions" option in the netlisting options form if you use this.
(See: AMS Environment Users Guide, Ch. 4, for more on this)

Hope this helps,

Han.

--
Han Speek
E-mail: Han.Speek@philips.N0SP@M.com (Remove .N0SP@M to reply)

 

[Han Speek]

Erik Wanta wrote:

Han:
I am told by Cadence that if I run ncvlog without the -ams option it
will ignore the following in the terminal declarations:
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)

I don't think design compiler with synthesis with this syntax however.
They are saying to use // synopsys translate_off and // synopsys
translate_on but then I would need 2 sections of terminal
declarations. I would need 2 sections of terminal declarations if
conditional compiles where used also.

Do I need to declare the electrical statements here or is there a way
that I can get these definitions in the cds_globals somehow with
HED->AMS->Globals?
---
Erik

Hi Eric,

It looks as if the (*... *) is treated as comment by any of the digital
NC tools - but I'm not too sure (haven't tested) if that works for
Synopsys
too.

I would say in this situation it's preferable to use the `ifdef INCA ...
`endif construct instead of the translate_off/translate_on, as you're
talking about NC tools specific enhancements thay you don't want any
(not just Synopsys) other tool to see.

But I don't see a way around having 2 sections of terminal declarations.

Regarding your last question, I have declared the global signals as wire
in the library cells (so they don't occur in the terminal list for the
cell), and declared them as electrical in the global signals setup in
the
Hierarchy Editor.

Regards,

Han.

--
Han Speek
E-mail: Han.Speek@philips.N0SP@M.com (Remove .N0SP@M to reply)

 

[Andrew Beckett]

I've not tried this, but can't you do:

input
`ifdef INCA
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)
`endif
d0;

Since the code doesn't have to be on a single line, I'd have thought this
would work?

I'm pretty sure this should work, and would therefore avoid you having to
have two alternate input definitions.

Andrew.

On Tue, 13 Jan 2004 11:35:50 +0100, Han Speek <"Han.Speek"@philips.N0SP@M.com>
wrote:

Erik Wanta wrote:

Han:
I am told by Cadence that if I run ncvlog without the -ams option it
will ignore the following in the terminal declarations:
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)

I don't think design compiler with synthesis with this syntax however.
They are saying to use // synopsys translate_off and // synopsys
translate_on but then I would need 2 sections of terminal
declarations. I would need 2 sections of terminal declarations if
conditional compiles where used also.

Do I need to declare the electrical statements here or is there a way
that I can get these definitions in the cds_globals somehow with
HED->AMS->Globals?
---
Erik


Hi Eric,

It looks as if the (*... *) is treated as comment by any of the digital
NC tools - but I'm not too sure (haven't tested) if that works for
Synopsys
too.

I would say in this situation it's preferable to use the `ifdef INCA ...
`endif construct instead of the translate_off/translate_on, as you're
talking about NC tools specific enhancements thay you don't want any
(not just Synopsys) other tool to see.

But I don't see a way around having 2 sections of terminal declarations.

Regarding your last question, I have declared the global signals as wire
in the library cells (so they don't occur in the terminal list for the
cell), and declared them as electrical in the global signals setup in
the
Hierarchy Editor.

Regards,

Han.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Andrew Beckett]

In fact I tried using this technique to add an attribute on an input in a
general module - I didn't really test it fully because I didn't have an
appropriate example, but clearly nc was compiling the attribute because it
spotted a typo in my attribute definition when I first attempted it.

So I think this should be OK. I'm out of the office, so didn't have time
to do a complete test. Erik, perhaps you could try this out and see if
it solves your problem and let us know?

Regards,

Andrew.

On Tue, 13 Jan 2004 17:03:47 +0000, Andrew Beckett
<andrewb@DELETETHISBITcadence.com> wrote:

I've not tried this, but can't you do:

input
`ifdef INCA
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)
`endif
d0;

Since the code doesn't have to be on a single line, I'd have thought this
would work?

I'm pretty sure this should work, and would therefore avoid you having to
have two alternate input definitions.

Andrew.

On Tue, 13 Jan 2004 11:35:50 +0100, Han Speek <"Han.Speek"@philips.N0SP@M.com
wrote:

Erik Wanta wrote:

Han:
I am told by Cadence that if I run ncvlog without the -ams option it
will ignore the following in the terminal declarations:
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)

I don't think design compiler with synthesis with this syntax however.
They are saying to use // synopsys translate_off and // synopsys
translate_on but then I would need 2 sections of terminal
declarations. I would need 2 sections of terminal declarations if
conditional compiles where used also.

Do I need to declare the electrical statements here or is there a way
that I can get these definitions in the cds_globals somehow with
HED->AMS->Globals?
---
Erik


Hi Eric,

It looks as if the (*... *) is treated as comment by any of the digital
NC tools - but I'm not too sure (haven't tested) if that works for
Synopsys
too.

I would say in this situation it's preferable to use the `ifdef INCA ...
`endif construct instead of the translate_off/translate_on, as you're
talking about NC tools specific enhancements thay you don't want any
(not just Synopsys) other tool to see.

But I don't see a way around having 2 sections of terminal declarations.

Regarding your last question, I have declared the global signals as wire
in the library cells (so they don't occur in the terminal list for the
cell), and declared them as electrical in the global signals setup in
the
Hierarchy Editor.

Regards,

Han.

--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd

 

[Erik Wanta]

Han:
I am told by Cadence that if I run ncvlog without the -ams option it
will ignore the following in the terminal declarations:
(* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *)

I don't think design compiler with synthesis with this syntax however.
They are saying to use // synopsys translate_off and // synopsys
translate_on but then I would need 2 sections of terminal
declarations. I would need 2 sections of terminal declarations if
conditional compiles where used also.

Do I need to declare the electrical statements here or is there a way
that I can get these definitions in the cds_globals somehow with
HED->AMS->Globals?
---
Erik



Han Speek <"Han.Speek"@philips.N0SP@M.com> wrote in message news:<3fe95a2c$0$279$4d4ebb8e@read-nat.news.nl.uu.net>...

Erik Wanta wrote:

I want to use supply sensitive interface elements. For verilog-AMS, I
add the following syntax to the code to make it supply sensitive.
What if I want to simulate both RTL and verilog-AMS code and still use
supply sensitive interface elements? That is, is there a way to use
the supply sensitive syntax in the RTL code and have it be used when
running AMS Designer and ignored if I am just running nc-verilog?

// define pin sensitivities
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d0;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) sl;
input (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) d1;
output (* integer supplySensitivity = "\\vdd! ";
integer supplySensitivity = "\\vss! "; *) x;

// supply declarations for supply sensitivity
electrical (* integer inh_conn_prop_name="vdd" ;
integer inh_conn_def_value="cds_globals.\vdd! "; *)
\vdd! ;
electrical (* integer inh_conn_prop_name="vss" ;
integer inh_conn_def_value="cds_globals.\vss! "; *)
\vss! ;

---
Erik

Hi Erik,

You can include the parts you don't want nc-verilog to see in pairs of
`ifdef INCA
...
`endif
conditionals.
However, don't forget to check the "Conditionally include language
extensions" option in the netlisting options form if you use this.
(See: AMS Environment Users Guide, Ch. 4, for more on this)

Hope this helps,

Han.