Suggestions/Recommendations with CPLD's and Software

[Henry]

I'm looking for some suggestions/recommendations with CPLD's and development
software.



I'm new to CPLD's and a couple projects of mine will involve redesigning
existing "though hole" hardware using a CPLD. I've researching some Xilinx
products, and believe the 9500 series will do everything I need, as my needs
really aren't that great. My only issue with the ISE software is I need to
recreate all the TTL IC logic from scratch, which will prove to be very time
consuming. I was hoping to find a design package that would already have
existing "groups" of TTL logic designed so I won't have to take as much time
with the schematic design and layout. For example in ISE it took me about
15 minutes just to draw the logic to a 74LS245. Only took me 3 minutes to
"wire" it up.



Any recommendations on other companies, other software and your experiences
with them would be appreciated.



Thanks for your time.





Henry

GSE-Reactive.com

My email is listed on the site if you wish to contact me directly.

 

[Zara]

On Mon, 7 Nov 2005 20:05:43 -0500, "Henry" <apl2research@comcast.net>
wrote:

I'm looking for some suggestions/recommendations with CPLD's and development
software.



I'm new to CPLD's and a couple projects of mine will involve redesigning
existing "though hole" hardware using a CPLD. I've researching some Xilinx
products, and believe the 9500 series will do everything I need, as my needs
really aren't that great. My only issue with the ISE software is I need to
recreate all the TTL IC logic from scratch, which will prove to be very time
consuming. I was hoping to find a design package that would already have
existing "groups" of TTL logic designed so I won't have to take as much time
with the schematic design and layout. For example in ISE it took me about
15 minutes just to draw the logic to a 74LS245. Only took me 3 minutes to
"wire" it up.



Any recommendations on other companies, other software and your experiences
with them would be appreciated.

Dont write the TTL logic with an schematic, it is best to write the
VHDL describing the function intended.

For instance,

architecture

entity ic74ls245 is
port (
A: inout std_logic_vector[1 to 4];
B: inout std_logic_vector[1 to 4];
DIR : in std_logic;
nOE : in std_logic
);

architecture Behavioral of ic74ls245 is
signal inA,inB : in std_logi';
sigbal A2B,B2A : std_logic_vector[1 to 4];

begin
-- output enable calculations
inA<=nOE or (not DIR);
inB<=nOE or DIR;

-- port A
pA:for i in A'range generate
pAbit:IOBUF(I=>B2A(i),O=>A2B(i),T=>inA,IO=>A(i));
end generate;

-- port B
pB:for i in B'range generate
pBbit:IOBUF(I=>A2B(i),O=>B2A(i),T=>inB,IO=>B(i));
end generate;

end Behavioral;

Time to write: 3 minutes, including the downloading from the Web of
the 74ls245 pdf datasheet.

Not tested, but most probably it is bug-free

Regards,

-- Zara

 

[krby_xtrm]

Since you'll be using Xilinx CPLD's you should use ISE, but if you dont
like to use ISE i recommend using Active-HDL then, its a very robust
HDL Development Environment such that it can invoke Xilinx Tools and
Synthesis/Implementation. Furthermore, with Active-HDL you can compile
your Designs using other Sythesis/Implementation like Altera's
Quartus-II Synthesis/Implementation tool. It means that your designs
will be vendor independent later on.

 

[john Doef]

Zara a écrit :

On Mon, 7 Nov 2005 20:05:43 -0500, "Henry" <apl2research@comcast.net
wrote:

I'm looking for some suggestions/recommendations with CPLD's and development
software.
[...]
For instance,

architecture

entity ic74ls245 is
port (
A: inout std_logic_vector[1 to 4];
B: inout std_logic_vector[1 to 4];
DIR : in std_logic;
nOE : in std_logic
);
[...]
Not tested, but most probably it is bug-free
You'd better to test it, because it is *not* bug free.

For example, index constraints should be (1 to 4) instead of [1 to 4].

JD.

 

[Zara]

On 8 Nov 2005 05:43:23 -0800, "john Doef" <john_doef@yahoo.com> wrote:

Zara a écrit :

On Mon, 7 Nov 2005 20:05:43 -0500, "Henry" <apl2research@comcast.net
wrote:

I'm looking for some suggestions/recommendations with CPLD's and development
software.
[...]
For instance,

architecture

entity ic74ls245 is
port (
A: inout std_logic_vector[1 to 4];
B: inout std_logic_vector[1 to 4];
DIR : in std_logic;
nOE : in std_logic
);
[...]
Not tested, but most probably it is bug-free
You'd better to test it, because it is *not* bug free.
For example, index constraints should be (1 to 4) instead of [1 to 4].

JD.

Yes, certainly, I was in a hurry. And I am really fed up with changing
my ming between C, C++ and VHDL. How I wish VHDL had used [] instead
of (), my life would have been less miserable.

Thanks for the correction!

-- Zara