Subtle interaction between force and tran

[Stephen Williams]

Here's an interesting puzzle. The following bit of Verilog is
pretty easy to predict:

reg a = 0, b = 1;
assign (weak0, weak1) x = a;
assign y = b;
tran (x,y);

In this case, x and y are strong 1 because the strength resolution
of the tran switch blends the strong-1 driving y and weak-0 driving
x to strong-1.

But at this to the mix:

initial #1 force x = 1;

Now what? ModelSim and NC-Verilog will give x===1'b1 and y==1'bx.
VCS will give x===y===1'b1. Who's right? And why?

I've attached a slightly more complete example. The attached
program prints PASSED when run by ModelSim, something else when
run by VCS. Personally, I prefer the VCS result as it preserves
the invariant of the tran() device. Any other result seems to
just reflect quirks in the implementations of "force".

Thoughts?

(I'm trying to get Icarus Verilog to do the "Right Thing" here,
but of course that means I have to pin down exactly what that
"Right Thing" really is.)

--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

On May 4, 3:12 pm, Stephen Williams <spamt...@icarus.com> wrote:

Now what? ModelSim and NC-Verilog will give x===1'b1 and y==1'bx.
VCS will give x===y===1'b1. Who's right? And why?

There seems to be some confusion here in your description.
NC-Verilog gives x===1 and y===1 in the situation you have
described. Nor would it make any sense for y to be unknown
in the situation you describe. Without the force it is 1,
and adding a force of 1 to the network can't make it less 1.

Perhaps the confusion is because your longer testcase inverts
the value of a when driving it onto x.

A more likely situation for a difference is if you force 0
onto x. If the force were only applied to the final value of
x, and the tran ignored it, then you would get y==1. If
the tran accounts for the fact that the value of x is 0, then
you get y==1'bx.

I am going to assume that this is the actual situation.

Since a force represents something that has no exact physical
analog, it is hard to make a perfect argument about what the
"right" behavior is. But surely if the force causes x to have
the value Strong0, the tran should not be acting as if it were
still a Weak0?

The LRM does not describe the exact behavior of forces and/or
trans in sufficient detail to address this question. But we
can turn to the de facto standard that it was based on.
Verilog-XL gives the same result as NC-Verilog in this case,
and also prints PASSED in your longer testcase. That tells
you that this is the "right" answer.

It sounds like VCS is taking short-cuts and only applying the
force to the final value of the net ("effective value" in VHDL
terms). It is failing to account for the fact that the net is
also an input to the tran, applied before final resolution, so
forces should affect the tran as they do any other input. It
takes special treatment to get forces right with trans. You
have to apply it to both the net's contribution to the tran,
and to the final resolution.

I've attached a slightly more complete example. The attached
program prints PASSED when run by ModelSim, something else when
run by VCS. Personally, I prefer the VCS result as it preserves
the invariant of the tran() device. Any other result seems to
just reflect quirks in the implementations of "force".

I am not sure what you mean by preserving the invariant. The VCS
value for the other side does not seem to match what would be
there if the forced value were applied "naturally".

The behavior of Verilog-XL and NC-Verilog (and presumably ModelSim)
results from deliberate special treatment required to get the right
answer. The behavior of VCS seems to be what falls out if you don't
apply special treatment to get it right.