sub modules

[mmt1]

Hello,
I've written a Verilog code which contains some sub modules. I change
one of them (because it wasn't synthesizable), in the manner that the
output of new sub module is equal to the output of old sub module. But
in this case, another sub module that is placed after changed sub
module, doesn't work truly. I don't know why it is happened. Can
any one help me?
Thanks a lot.

 

[unfrostedpoptart]

mmt1 wrote:

I've written a Verilog code which contains some sub modules. I change
one of them (because it wasn't synthesizable), in the manner that the
output of new sub module is equal to the output of old sub module. But
in this case, another sub module that is placed after changed sub
module, doesn't work truly. I don't know why it is happened. Can
any one help me?

No one can help if you don't give any information. You need to post
your code and simulator messages.

David

 

[Ajeetha]

Hi,

mmt1 wrote:

Hello,
I've written a Verilog code which contains some sub modules. I change
one of them (because it wasn't synthesizable), in the manner that the
output of new sub module is equal to the output of old sub module.

How did you verify that these 2 modules produce *same* result? If the
model is simple enough, can you show the code?

But
in this case, another sub module that is placed after changed sub
module, doesn't work truly. I don't know why it is happened. Can

As a wild guess, your "changed sub module" is misbehaving. May be you
can generate waveform for both cases and compare them. Another option
is to instantiate both "old" and "new" modules and do an XOR kind of
check bet'n these 2 module outputs at the system level. One could also
use Equiv. checking, but that will require your models to be
synthesisable - which it is not.

Regards
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
www.systemverilog.us
* SystemVerilog Assertions Handbook
* Using PSL/Sugar

any one help me?
Thanks a lot.

 

[Enchanter]

Can formal check find the problem?


mmt1 wrote:

Hello,
I've written a Verilog code which contains some sub modules. I change
one of them (because it wasn't synthesizable), in the manner that the
output of new sub module is equal to the output of old sub module. But
in this case, another sub module that is placed after changed sub
module, doesn't work truly. I don't know why it is happened. Can
any one help me?
Thanks a lot.