Style question - leftshift or not?

[Paul Marciano]

Hi,

In terms of style/synthesis is there any reason to prefer:

reg [5:0] v;
wire sig;

v <= { v[4:0], sig };

over:

v <= (v << 1) | sig;


I believe these are equivalent.

Regards,
Paul.

 

[Jason Zheng]

Paul Marciano wrote:

Hi,

In terms of style/synthesis is there any reason to prefer:

reg [5:0] v;
wire sig;

v <= { v[4:0], sig };

over:

v <= (v << 1) | sig;


I believe these are equivalent.

Regards,
Paul.

They are not equivalent when v is 6'bz. The former will give you
{5'bzzzzz, sig}, and the latter will give you {5'bxxxxx, sig}. I like
the former better because it's exactly what you want a shifter to do.

-z

 

[John_H]

They're equivalent. Sometimes it's more "effective" to communicate one
versus the other to communicate the functionality to other engineers. The
latter form is certainly preferred if the engineer (or the tool) could be
confused about what the width would be if the "sig" were an expression
rather than a wire/reg.

"Paul Marciano" <pm940@yahoo.com> wrote in message
news:1127755858.878564.293980@g44g2000cwa.googlegroups.com...

Hi,

In terms of style/synthesis is there any reason to prefer:

reg [5:0] v;
wire sig;

v <= { v[4:0], sig };

over:

v <= (v << 1) | sig;


I believe these are equivalent.

Regards,
Paul.

 

[Paul Marciano]

John/Jason,

Thanks once again for the replies - you two guys are a real help!

Jason Zheng wrote:

They are not equivalent when v is 6'bz. The former will give you
{5'bzzzzz, sig}, and the latter will give you {5'bxxxxx, sig}. I like
the former better because it's exactly what you want a shifter to do.

That's a very interesting point Jason. The behavior of 'z' didn't even
occur to me. Thanks.

Regards,
Paul.

 

[John Penton]

Paul Marciano wrote:

Hi,

In terms of style/synthesis is there any reason to prefer:

reg [5:0] v;
wire sig;

v <= { v[4:0], sig };

over:

v <= (v << 1) | sig;

In the first case, it is explicit that you are losing infomation (v[5]), but
in the second case this is less obvious. A linting tool will compain that
you are assigning a 7-bit value to a 6-bit signal in the second case. (It
will also complain that your OR operator has unequal sized operands). The
second case therefore relies on the truncation (and extension) behaviours of
verilog - which are not always entirely obvious.

I personally think that the first example is much more readable for a
constant shift.

John

--
John Penton, posting as an individual unless specifically indicated
otherwise.

 

[Paul Marciano]

John Penton wrote:

), but
in the second case this is less obvious. A linting tool will compain that
you are assigning a 7-bit value to a 6-bit signal in the second case. (It
will also complain that your OR operator has unequal sized operands). The
second case therefore relies on the truncation (and extension) behaviours of
verilog - which are not always entirely obvious.

Thanks John. I come from a 'C' background and shifting out of the end
of a register and promotion of narrow values to wider values when used
in arithmetic is something I tend to not be surprised by.

I agree that it's better to be explicit - to aid in readability.

Thanks for the insight.

Paul.