Style Question for Components

S

Shannon

Guest
Finally I have a STYLE question rather than a how-to!

So I'm putting together the top level of my hierarchical design. I
have many individual entities in my 'work' directory that I want to
hook together.

What is the "standard" that you synthisis guys use?

Declare - Instantiate - Configure a-la VHDL '87
or
direct instantiation a-la VHDL '93?

or something else?

Shannon
 
Shannon wrote:

What is the "standard" that you synthisis guys use?
Click to expand...
This guy uses

---------> direct instantiation a-la VHDL '93?

Here's an example from a testbench, but it's
the same format in synthesis structures.

-- Mike Treseler

dut : entity work.uart
port map (
clock => clk_s, -- [in] -- by tb_clk
reset => rst_s, -- [in] -- by tb_clk
address => address_s, -- [in] -- by main
writeData => writeData_s, -- [in] -- by main
write_stb => write_stb_s, -- [in] -- by main
readData => readData_s, -- [out]-- by uut
read_stb => read_stb_s, -- [in] -- by main
serialIn => serialIn_s, -- [in] -- by main,loopback dest
serialOut => serialOut_s -- [out]-- by uut, loopback source
);


-- Mike Treseler
 
Shannon <sgomes@sbcglobal.net> writes:

Finally I have a STYLE question rather than a how-to!

So I'm putting together the top level of my hierarchical design. I
have many individual entities in my 'work' directory that I want to
hook together.

What is the "standard" that you synthisis guys use?

Hi Shannon,
Click to expand...

My answer would be direct instantiation (unless you have a really good
reason not to).

We had a thread about this a while ago: (sorry, long line!)
http://groups.google.co.uk/group/comp.lang.vhdl/browse_thread/thread/654bdc63363fe3ed/f661479f1ba38b61?lnk=st&q=vhdl+direct+instantiation&rnum=1&hl=en#f661479f1ba38b61

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
 
I'm with Mike, except I also declare the architecture name, as
follows:

dut : entity work.uart(rtl)

where "rtl" is the name of an architecture for the entity uart.
Otherwise, the least recently analyzed architecture gets used, just
like with components and default bindings.

Note that direct instantiation requires strict order of compilation,
which with most tools is a very small price to pay for having no
configurations and no components to mess with (nor the uncertainties
of default bindings)*.

* the language is not uncertain WRT default bindings, but I usually
am!

Andy
 
Thanks for the replies all. Looks like direct instantiation is the
winner.

Andy, you mentioned strict order of compilation is required. Can you
elaborate?

Shannon
 
On Sep 6, 10:03 am, Shannon <sgo...@sbcglobal.net> wrote:
Thanks for the replies all. Looks like direct instantiation is the
winner.

Andy, you mentioned strict order of compilation is required. Can you
elaborate?

Shannon
Click to expand...
No, elaboration is different from compilation (analysis) ;^)

Oh, you want more information on order of compilation...

When you compile an architecture with component instantiations, only
the component definition needs to be previously compiled (either in a
package, or in the declarative region of the instantiating
architecture itself). Subsequently, only if the component later
changes does the instantiating architecture have to be recompiled.

When you compile an architecture with a direct entity and architecture
instantiation, both the architecture and its entity must already be
compiled (naturally, the entity before its architecture).
Subsequently, any change to the entity or architecture will force a
recompile on the instantiating architecture.

If the architecture is not indicated explicitly in an entity
instantiation, then only entity changes (which would likely have
caused the component to change also, had there been one) require the
instantiating architecture to be recompiled. But the entity must have
been compiled first before the instantiating architecture.

For most tools, this is not a big problem, since they tend to take
care of knowing when to compile what, once the design is compiled
correctly the first time. Some tools allow you to just throw a list of
files at them (in any order), and they will parse them and figure out
the correct order (you have to tell them the top level usually). They
can even correctly compile modules that occur out of order in the same
file.

Clear as mud?

Andy
 
Um, what?

My spell checker says those were all english words but I don't think
I've ever seen them in that particular order before.

Shannon
 
Shannon wrote:
Um, what?
Click to expand...
Compile
my_entity
before compiling
my_instance: work.my_entity(synth)

"before" might mean in the file before
or in a line above.

-- Mike Treseler
 
On Sep 7, 10:07 am, Mike Treseler <mike_trese...@comcast.net> wrote:
Shannon wrote:
Um, what?

Compile
my_entity
before compiling
my_instance: work.my_entity(synth)

"before" might mean in the file before
or in a line above.

-- Mike Treseler
Click to expand...
Got it. Thanks Mike.

Andy: I hope you took my response in the right light. I thank you for
your response. I was being a bit "cheeky" with my response. I really
did have to read it through about ten times before I got it.

Shannon
 
On Sep 7, 1:55 pm, Shannon <sgo...@sbcglobal.net> wrote:
On Sep 7, 10:07 am, Mike Treseler <mike_trese...@comcast.net> wrote:

Shannon wrote:
Um, what?

Compile
my_entity
before compiling
my_instance: work.my_entity(synth)

"before" might mean in the file before
or in a line above.

-- Mike Treseler

Got it. Thanks Mike.

Andy: I hope you took my response in the right light. I thank you for
your response. I was being a bit "cheeky" with my response. I really
did have to read it through about ten times before I got it.

Shannon
Click to expand...
You didn't want me to just GIVE you the answer, did you? ;^)

Andy
 
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