Stupid question

[Thomas Womack]

Is there a better Verilog sequence for the polynomial-multiplier

begin
C[10:0] <= A[10:0] & {B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0]};
C[11:1] <= C[11:1] ^ (A[10:0] & {B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1]});
....

C[20:10] <= ...
end

or should I be writing Perl to generate the rather stereotyped code above?

What if I want a polynomial-multiplier of user-definable width?

Tom

 

[Jonathan Bromley]

On 28 Apr 2004 15:09:25 +0100 (BST), Thomas Womack
<twomack@chiark.greenend.org.uk> wrote:

Is there a better Verilog sequence for the polynomial-multiplier

begin
C[10:0] <= A[10:0] & {B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0]};
C[11:1] <= C[11:1] ^ (A[10:0] & {B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1]});
...

I really don't think you mean quite that. Maybe if the
assignments were blocking, instead? (always assuming you're
trying to do the whole thing in one clock cycle)

This sounds a bit nicer... it depends on the fact that
XORing with zero has no effect. Some details missing,
of course.

reg [20:0] C;
reg [10:0] A, B;
integer i;
...
C = 0;
for (i=0; i<=10; i=i+1) begin
if (B) begin
C = C ^ (A << I);
end
end // for

or should I be writing Perl to generate the rather stereotyped code above?

Maybe... not for my taste, though.

The form

A[10:0] & {B[1], B[1] ....}

is easily rewritten using a conditional expression:

B[1] ? A[10:0] : 11'b0

What if I want a polynomial-multiplier of user-definable width?

I think the version I offered could easily be modified
so that it's parameterised.
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[John_H]

If you just want to avoid the manual replication in the concatenated vector,
use the replicate {{ }}:

C[10:0] <= ( A[10:0] & {11{B[0]}} );
C[11:1] <= ( A[10:0] & {11{B[1]}} ) ^ C[11:1];

or use the conditional operator

C[10:0] <= ( B[0] ? A[10:0] : 11'h000 );
C[11:1] <= ( B[1] ? A[10:0] : 11'h000 ) ^ C[11:1];


"Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message
newstb*f7+iq@news.chiark.greenend.org.uk...

Is there a better Verilog sequence for the polynomial-multiplier

begin
C[10:0] <= A[10:0] &
{B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0]};
C[11:1] <= C[11:1] ^ (A[10:0] &
{B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1],B[1]});
...

C[20:10] <= ...
end

or should I be writing Perl to generate the rather stereotyped code above?

What if I want a polynomial-multiplier of user-definable width?

Tom

 

[Petter Gustad]

Thomas Womack <twomack@chiark.greenend.org.uk> writes:

Is there a better Verilog sequence for the polynomial-multiplier

begin
C[10:0] <= A[10:0] & {B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0],B[0]};

C[10:0] <= A[10:0] & {11{B[0]}};

is a shorter way of writing this expression.


Petter
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