Study material for logic design

Hi All Verilog users:

I am trying to find some study material to cover the basics of logic
design. Actually I am preparing for an interview. Can anyone of you
point to me some material online or forward me any documents that you
have in some of the topics of logic design i.e.

- Timing issues with a logic delay block sandwiched between two flip
flops etc
- Setup and hold time concepts and formulas
- Metastability etc
- General timing issues and faced in logic design synthesis

Your feedback will be greatly appreciated.

Regards,

Salah
salah.kazi @ gmail . com
salah.kazi@gmail.com


--
Salahuddin (Salah) Kazi
(416) 716-5634 (Cell), (905) 472-8890 (Home)
Fax: (905) 201-8850, salah.kazi@gmail.com
http://salahkazi.tripod.com/resume.htm

 

[Fazela]

Hi Salah,
You might want to refer to handouts of the VLSI Design Class on Dr.
Jim's webpage from UMBC
http://www.csee.umbc.edu/~plusquel/
as also the logic design handouts on Dr. Thorton's webpage on
http://engr.smu.edu/~mitch
I have always found these sources to be very good.

-FV

 

[Salah]

Thanks Fazela.

Salah