structural programing

[valli]

Hi,

I am novice to VHDL. When I am trying compile a program in
structural modal it compiles well for first time but next day I got
error "vhdlfe: andor.vhd: Abort: (E39) Need to recompile
'C:\warp\examples\project2\andor.vhd'." .

Here is my code:
It is simple and or gate. I wrote vhdl code for 'and' in one file and
code for 'or' in another file. I used these two as components in
another file name 'andor.vhd'.

Here is my code:

library ieee; -- component #1
use ieee.std_logic_1164.all;

entity AND_GATE is
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end AND_GATE;

architecture behv of AND_GATE is
begin
process(A,B)
begin
F1 <= A and B; -- behavior des.
end process;
end behv;

library ieee; -- component #2
use ieee.std_logic_1164.all;

entity OR_GATE is
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end OR_GATE;

architecture behv of OR_GATE is
begin
process(X,Y)
begin
F2 <= X or Y; -- behavior des.
end process;
end behv;

library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;

entity comb_ckt is
port( input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
output: out std_logic
);
end comb_ckt;

architecture struct of comb_ckt is

component AND_GATE -- as entity of AND_GATE
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end component;

component OR_GATE -- as entity of OR_GATE
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end component;


for Gate1: AND_GATE
use entity work.AND_GATE(behv)
port map(A,B,F1);

for Gate2: OR_GATE
use entity work.OR_GATE(behv)
port map (X,Y,F2);

signal wire: std_logic;

begin


Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);

end struct;


Could any one tell me why I am getting like this and suggest any
modifications for this program.

 

[Paul Uiterlinden]

valli wrote:

Hi,

I am novice to VHDL. When I am trying compile a program in
structural modal it compiles well for first time but next day I got
error "vhdlfe: andor.vhd: Abort: (E39) Need to recompile
'C:\warp\examples\project2\andor.vhd'." .

Here is my code:
It is simple and or gate. I wrote vhdl code for 'and' in one file and
code for 'or' in another file. I used these two as components in
another file name 'andor.vhd'.

I guess the order in which you compile is wrong. First compile the files
containing 'and' and 'or', then the file containing 'andor'.

Also, I would suggest using a configuration declaration in stead of
configuration specifications:

CONFIGURATION cmb_ckt_cfg OF cmb_ckt IS
FOR struct;
FOR gate1: and_gate
USE ENTITY work.and_gate(behv);
END FOR;
FOR gate2: or_gate
USE ENTITY work.or_gate(behv);
END FOR;
END FOR
END CONFIGURATION cmb_ckt_cfg;

This would replace the two configuration specifications that are now in
your architecture.

Having said that, you might leave out the configuration stuff
altogether, as synthesizers often do not support them.

Paul.

 

[Jim Lewis]

valli
Some synthesis tools don't like configurations.
The easy solution is to remove it as a component
will bind by default to an entity of the same name.
So remove the following:

for Gate1: AND_GATE
use entity work.AND_GATE(behv)
port map(A,B,F1);

for Gate2: OR_GATE
use entity work.OR_GATE(behv)
port map (X,Y,F2);

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I am novice to VHDL. When I am trying compile a program in
structural modal it compiles well for first time but next day I got
error "vhdlfe: andor.vhd: Abort: (E39) Need to recompile
'C:\warp\examples\project2\andor.vhd'." .

Here is my code:
It is simple and or gate. I wrote vhdl code for 'and' in one file and
code for 'or' in another file. I used these two as components in
another file name 'andor.vhd'.

Here is my code:

library ieee; -- component #1
use ieee.std_logic_1164.all;

entity AND_GATE is
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end AND_GATE;

architecture behv of AND_GATE is
begin
process(A,B)
begin
F1 <= A and B; -- behavior des.
end process;
end behv;

library ieee; -- component #2
use ieee.std_logic_1164.all;

entity OR_GATE is
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end OR_GATE;

architecture behv of OR_GATE is
begin
process(X,Y)
begin
F2 <= X or Y; -- behavior des.
end process;
end behv;

library ieee; -- top level circuit
use ieee.std_logic_1164.all;
use work.all;

entity comb_ckt is
port( input1: in std_logic;
input2: in std_logic;
input3: in std_logic;
output: out std_logic
);
end comb_ckt;

architecture struct of comb_ckt is

component AND_GATE -- as entity of AND_GATE
port( A: in std_logic;
B: in std_logic;
F1: out std_logic
);
end component;

component OR_GATE -- as entity of OR_GATE
port( X: in std_logic;
Y: in std_logic;
F2: out std_logic
);
end component;


for Gate1: AND_GATE
use entity work.AND_GATE(behv)
port map(A,B,F1);

for Gate2: OR_GATE
use entity work.OR_GATE(behv)
port map (X,Y,F2);

signal wire: std_logic;

begin


Gate1: AND_GATE port map (A=>input1, B=>input2, F1=>wire);
Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);

end struct;


Could any one tell me why I am getting like this and suggest any
modifications for this program.