Strings in Verilog

T

trescot@gmail.com

Guest
How can we represent the following line in Verilog?

type STR4_ARRAY is array (2 downto 0) of string(1 to 4);


Actually its a part of a VHDL tb code. It seems that the owner of the
code has used "type" to declare the strings which are basically state
mnemonics. He also displays the string in the waveforms. He is also
doing some encodings from these strings.

Is same kind of operation possible using Verilog? When I try to do
something like

reg [8*4:0] string ; ---> It just gives me the ascii value not the
strings.


Thanks
Trescot
 
trescot@gmail.com wrote:
How can we represent the following line in Verilog?

type STR4_ARRAY is array (2 downto 0) of string(1 to 4);


Actually its a part of a VHDL tb code. It seems that the owner of the
code has used "type" to declare the strings which are basically state
mnemonics. He also displays the string in the waveforms. He is also
doing some encodings from these strings.

Is same kind of operation possible using Verilog? When I try to do
something like

reg [8*4:0] string ; ---> It just gives me the ascii value not the
strings.


Thanks
Trescot

Srings in Verilog are not treated any differently than other types. You
Click to expand...
can use a register as a string like this:

reg [32*8-1:0] string = "Hello World"; // 32-char string
initial $display ("The string is %s",string);

You can use this to assign string names to states for display in a
simulator. To display a string name in the Modelsim wave window, set
the radix of the wave to ASCII; otherwise it will just show up as a hex
value. The simulator doesn't know automatically that the value is meant
to be a string.

If your tools support SystemVerilog, I recommend the use of the
enumerated types for state names.
-Kevin
 
On Sep 17, 3:35 pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
tres...@gmail.com wrote:
How can we represent the following line in Verilog?

type STR4_ARRAY is array (2 downto 0) of string(1 to 4);

Actually its a part of a VHDL tb code. It seems that the owner of the
code has used "type" to declare the strings which are basically state
mnemonics. He also displays the string in the waveforms. He is also
doing some encodings from these strings.

Is same kind of operation possible using Verilog? When I try to do
something like

reg [8*4:0] string ; ---> It just gives me the ascii value not the
strings.

Thanks
Trescot

Srings in Verilog are not treated any differently than other types. You
can use a register as a string like this:

reg [32*8-1:0] string = "Hello World"; // 32-char string
initial $display ("The string is %s",string);

You can use this to assign string names to states for display in a
simulator. To display a string name in the Modelsim wave window, set
the radix of the wave to ASCII; otherwise it will just show up as a hex
value. The simulator doesn't know automatically that the value is meant
to be a string.

If your tools support SystemVerilog, I recommend the use of the
enumerated types for state names.
-Kevin
Click to expand...

I have a procedure in VHDL which basically converts an integer to
string data and then concatenate it with another string to form an ID
shown as below.

ID = "S"+ Int2str(Din,Dout); // function call where ID is string
data

// Actual Function
procedure Int2str( Din : in integer range 0 to 9;
Dout : out string
) is


type DIGIT_2_CHAR is array(0 to 9) of character;
constant to_char : DIGIT_2_CHAR := ('0','1','2','3','4',
'5','6','7','8','9');
begin
Dout := to_char(Din);
end Int2str


I have no idea how this can be implemented in Verilog as there is no
"type" in Verilog. I tried something like this but it didn't work.

reg [(8*1)-1:0] Din ;

Dout = "Din" ; // it will show Din, but not the actual value
// if I try Dout = Din its giving junk data.

So how can I concatenate string with integer and treat the output as
string.


Thanks
 
trescot@gmail.com wrote:
On Sep 17, 3:35 pm, Kevin Neilson
kevin_neil...@removethiscomcast.net> wrote:
tres...@gmail.com wrote:
How can we represent the following line in Verilog?
type STR4_ARRAY is array (2 downto 0) of string(1 to 4);
Actually its a part of a VHDL tb code. It seems that the owner of the
code has used "type" to declare the strings which are basically state
mnemonics. He also displays the string in the waveforms. He is also
doing some encodings from these strings.
Is same kind of operation possible using Verilog? When I try to do
something like
reg [8*4:0] string ; ---> It just gives me the ascii value not the
strings.
Thanks
Trescot
Srings in Verilog are not treated any differently than other types. You
can use a register as a string like this:

reg [32*8-1:0] string = "Hello World"; // 32-char string
initial $display ("The string is %s",string);

You can use this to assign string names to states for display in a
simulator. To display a string name in the Modelsim wave window, set
the radix of the wave to ASCII; otherwise it will just show up as a hex
value. The simulator doesn't know automatically that the value is meant
to be a string.

If your tools support SystemVerilog, I recommend the use of the
enumerated types for state names.
-Kevin


I have a procedure in VHDL which basically converts an integer to
string data and then concatenate it with another string to form an ID
shown as below.

ID = "S"+ Int2str(Din,Dout); // function call where ID is string
data

// Actual Function
procedure Int2str( Din : in integer range 0 to 9;
Dout : out string
) is


type DIGIT_2_CHAR is array(0 to 9) of character;
constant to_char : DIGIT_2_CHAR := ('0','1','2','3','4',
'5','6','7','8','9');
begin
Dout := to_char(Din);
end Int2str


I have no idea how this can be implemented in Verilog as there is no
"type" in Verilog. I tried something like this but it didn't work.

reg [(8*1)-1:0] Din ;

Dout = "Din" ; // it will show Din, but not the actual value
// if I try Dout = Din its giving junk data.

So how can I concatenate string with integer and treat the output as
string.


Thanks


Here's a way to convert an integer to a string and to concatenate it
Click to expand...
with the letter "s":

module strconcat();
reg [8*32-1:0] String;
parameter DIGITS = "9876543210";
integer din;
initial
begin
din = 4;
String = {"S",DIGITS[din*8+:8]};
$display ("The concatenated string is %s",String);
end
endmodule

results:

vsim> run
# The concatenated string is S4

I think "string" is a reserved word in SystemVerilog which is why I
capitalized it. The conversion just uses din as an index into the
80-bit array DIGITS and extracts eight bits to concatenate with "S".
-Kevin
 
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