S
Shannon
Guest
I've been searching here but all the hits were for converting SLV to
string for testbenches.
I'm looking to convert a string to an array of 8bit SLVs. The idea is
I have a revision string of fixed length- something like:
ver <= "005-0805300908x2"'
and I have an array of registers declared as such:
SUBTYPE hwid_type is STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type;
SIGNAL regs : reg_type;
What I'm looking for is a loop shown here in psuedo code:
for i in 1 to 16 loop
regs(i) <= to_slv(ver(mid$(i,1)))
end loop
Note this is for synthesis so I don't know if any of this is even
legal. I am trying to create a version register that the
microprocessor can read. An ascii string is prefered - let's pretend
for a moment it is a requirement. This is also a learning exercise
for me to deal with strings in VHDL.
Any ideas?
Shannon
string for testbenches.
I'm looking to convert a string to an array of 8bit SLVs. The idea is
I have a revision string of fixed length- something like:
ver <= "005-0805300908x2"'
and I have an array of registers declared as such:
SUBTYPE hwid_type is STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE reg_type IS ARRAY (0 TO NUM_REGS-1) OF hwid_type;
SIGNAL regs : reg_type;
What I'm looking for is a loop shown here in psuedo code:
for i in 1 to 16 loop
regs(i) <= to_slv(ver(mid$(i,1)))
end loop
Note this is for synthesis so I don't know if any of this is even
legal. I am trying to create a version register that the
microprocessor can read. An ascii string is prefered - let's pretend
for a moment it is a requirement. This is also a learning exercise
for me to deal with strings in VHDL.
Any ideas?
Shannon