S
Steve Casselman
Guest
Hey check out www.stretchinc.com
Steve
Steve
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Ray Andraka
Guest
Steve,
I'm sure Jeff and his cohorts appreciate the plug... The
website says far more than they were willing to tell us last
week. BTW, we missed you at FCCM again this year.
Steve Casselman wrote:
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
I'm sure Jeff and his cohorts appreciate the plug... The
website says far more than they were willing to tell us last
week. BTW, we missed you at FCCM again this year.
Steve Casselman wrote:
--Hey check out www.stretchinc.com
Steve
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
J
Jim Granville
Guest
Ray Andraka wrote:
Does the EEMBC benchmark mean they have real silicon ?
On all other cores, I see (ASM OPT) gives quite a gain over (C OPT).
Thus on this core, could one expect (ASM + Floorplan OPT) to
also give gains ?
-jg
Looks interesting..Steve,
I'm sure Jeff and his cohorts appreciate the plug... The
website says far more than they were willing to tell us last
week. BTW, we missed you at FCCM again this year.
Steve Casselman wrote:
Hey check out www.stretchinc.com
Steve
Does the EEMBC benchmark mean they have real silicon ?
On all other cores, I see (ASM OPT) gives quite a gain over (C OPT).
Thus on this core, could one expect (ASM + Floorplan OPT) to
also give gains ?
-jg
J
Jim Granville
Guest
Jim Granville wrote:
http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=O2NAUQOWPWFSWQSNDBCCKHQ?articleID=19200029
Talks of dual port memory, 100MHz logic fabric speeds, and this
comment was the most revealing :
"When the compiler extracts and creates a custom pipeline, it also
works out the latency, so it knows how large a delay slot to insert in
the code stream for that operation."
So the PR talk of a 'single opcode' was only part of the story -
These HW assisted single opcodes can be quite slow (relative to other
single opcodes, but of course, still much faster than SW wheel spinning )
DMA reload in two halves in 80-100us also sounded good...
No sign yet of numbers showing just how big the ProgLogicFabric is ?
-jg
There is more info here :Looks interesting..
Does the EEMBC benchmark mean they have real silicon ?
On all other cores, I see (ASM OPT) gives quite a gain over (C OPT).
Thus on this core, could one expect (ASM + Floorplan OPT) to
also give gains ?
http://www.eet.com/semi/news/showArticle.jhtml;jsessionid=O2NAUQOWPWFSWQSNDBCCKHQ?articleID=19200029
Talks of dual port memory, 100MHz logic fabric speeds, and this
comment was the most revealing :
"When the compiler extracts and creates a custom pipeline, it also
works out the latency, so it knows how large a delay slot to insert in
the code stream for that operation."
So the PR talk of a 'single opcode' was only part of the story -
These HW assisted single opcodes can be quite slow (relative to other
single opcodes, but of course, still much faster than SW wheel spinning )
DMA reload in two halves in 80-100us also sounded good...
No sign yet of numbers showing just how big the ProgLogicFabric is ?
-jg