Streaming data to memory...

[Marwan]

Peace,

I am having a nightmare trying to find an answer to this question, but
its something easy if one knows...

I want to stream 'real-time' data from an external source into
memory...

But I am unsure as to how to do this...

The data will be coming in (alternatives being investigated, so answer
generally please) and the data will be in 12 bit samples.

A method of doing this will be having n bitstreams (as opposed to
buses) coming into a memory, so I will need to 'catch' the data on
each channel in a continuous manner.

So imagine.

Data rate = 2048samples/second => 12x2048bits/second

so do I have to sample the input ports of my module at 12x2048 and
catch every bit as it comes and shift it in/along? If so how?

Or can I just sample at 2048samples/second and do the following: -

{stripped down code}

set n to 32...

module ip_mem(port_in, clk, mem_out);
....
input wire port_in[0:31]; // 32 i/p ports
....

reg [11:0] mem1 [0:1023]; // input memory

reg clk; // 2048hz

always@(posedge clk)
begin
integer i;
for(i=0; i <= 31; i = i+1)
begin
mem[i*32 :i*32 + 31 ] = port_in; /* assigning port_in to 32 of
mem1's 12 bit registers. should I use mem[i*32 +: 32] instead?*/
end
end
endmodule

Any help would be great!

Peace,
Marwan

 

[John_H]

Your description isn't clear and your code makes things murkier.
Your port_in is 32 bits wide... for 32 serialized 12-bit channels?
You declare a 12-bit wide, 1024 deep mem but you're trying to assign the
entire port range to your mem as if it were a 12*1024 wide vector?
The port_in probably wants an on it where you make the assign.
The [i*32+:32] is the proper construct - you'll get errors with the other.
If you're bringing in the samples serially, I would think you'd want to use
a set of serial-in, parallel-out shift registers to store 12-bit words in a
memory array.

Do you have a clock accompanying your 32 channels of serial data?
Do you have a frame bit or other "start of data word" information?
Is your sample rate seriously only 2 kHz? Not 2 MHz or 2 GHz?

When do you start accumulating your real time data and when do you stop?
Will you be processing the data in real time such that you really want a
FIFO?

These questions and more...


"Marwan" <marwanboustany@gmail.com> wrote in message
news:1172262379.989381.17990@p10g2000cwp.googlegroups.com...

Peace,

I am having a nightmare trying to find an answer to this question, but
its something easy if one knows...

I want to stream 'real-time' data from an external source into
memory...

But I am unsure as to how to do this...

The data will be coming in (alternatives being investigated, so answer
generally please) and the data will be in 12 bit samples.

A method of doing this will be having n bitstreams (as opposed to
buses) coming into a memory, so I will need to 'catch' the data on
each channel in a continuous manner.

So imagine.

Data rate = 2048samples/second => 12x2048bits/second

so do I have to sample the input ports of my module at 12x2048 and
catch every bit as it comes and shift it in/along? If so how?

Or can I just sample at 2048samples/second and do the following: -

{stripped down code}

set n to 32...

module ip_mem(port_in, clk, mem_out);
...
input wire port_in[0:31]; // 32 i/p ports
...

reg [11:0] mem1 [0:1023]; // input memory

reg clk; // 2048hz

always@(posedge clk)
begin
integer i;
for(i=0; i <= 31; i = i+1)
begin
mem[i*32 :i*32 + 31 ] = port_in; /* assigning port_in to 32 of
mem1's 12 bit registers. should I use mem[i*32 +: 32] instead?*/
end
end
endmodule

Any help would be great!

Peace,
Marwan

 

[Marwan]

On Feb 23, 11:15 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

Your description isn't clear and your code makes things murkier.
Your port_in is 32 bits wide... for 32 serialized 12-bit channels?
You declare a 12-bit wide, 1024 deep mem but you're trying to assign the
entire port range to your mem as if it were a 12*1024 wide vector?
The port_in probably wants an on it where you make the assign.
The [i*32+:32] is the proper construct - you'll get errors with the other.
If you're bringing in the samples serially, I would think you'd want to use
a set of serial-in, parallel-out shift registers to store 12-bit words in a
memory array.

Do you have a clock accompanying your 32 channels of serial data?
Do you have a frame bit or other "start of data word" information?
Is your sample rate seriously only 2 kHz? Not 2 MHz or 2 GHz?

When do you start accumulating your real time data and when do you stop?
Will you be processing the data in real time such that you really want a
FIFO?

These questions and more...

I agree the description is not clear, but that is partially by design
as I am not clear on it and I don't want to detail a situation that
may not exist. So I just described generally the problem so the
solution could be general.

Your port_in is 32 bits wide... for 32 serialized 12-bit channels?

yes... i think.. I mean 32 channels with serialised data samples of
12 bit resolution. (as an example, can be more)

You declare a 12-bit wide, 1024 deep mem but you're trying to assign the
entire port range to your mem as if it were a 12*1024 wide vector?

I am not yet trying anything because I want to understand the method
before I code. I am merely asking questions on how to do something
(store in coming continuous data) and I gave two ideas in the hope of
suggestions or corrections to the ideas.

I declared (I believe) a 1024 address memory, where each memory is 12
bits wide. And in my example code, I wish to assign 32 12 bit samples
from the 32 port_in and so need 32x32 memory spaces.

I could code the memory as

reg [11:0] ip_mem [0:31] [0:31];

but then this could add the difficulty of having to shift the data
along as well as capturing and storing... but im open for
suggestions. But as yet i am unclear which is the easiest style for
the memory... I would like to use the 32x32 format if I can just call
it from another module, but if I have to send data from it through
output ports and input ports of modules, then the 1x1024 memory might
be easier... but as yet i'm not sure.

If you're bringing in the samples serially, I would think you'd want to use
a set of serial-in, parallel-out shift registers to store 12-bit words in a
memory array.

This sounds like a good idea... To clarify, Are you saying that I take
in the data bit by bit while shifting, and then take the data out of
the 12 bit section in parallel style?

Do you have a clock accompanying your 32 channels of serial data?

Not to my knowledge, I will know the sampling rate, and so can adjust
the internal clock as needed in the input memory or data acquisition
module.

Do you have a frame bit or other "start of data word" information?

Not that i can find any specifications for, and so I am working that
its just sample data with not start or end of word data.

Is your sample rate seriously only 2 kHz? Not 2 MHz or 2 GHz?

It may be more but not in the Mhz or Ghz range, as I am dealing with a
biomedical design...

When do you start accumulating your real time data and when do you stop?

The accumulation is continuous over a selected period, say 15 to 20
minutes.

Will you be processing the data in real time such that you really want a
FIFO?

Yes, the data must be processed in real time. As the data will be
worked on in blocks, I will be using a dual memory solution. Data
goes into memory 1, shifted into memory 2, data in memory 2 is worked
on as memory 1 is filled again etc... in a constant cycle.

To clarify... If data is coming in serially and continuously in a
real-time application, what is the best way to actually collect the
memory as it is coming in? bit by bit or word by word?

Peace,
Marwan

 

[John_H]

There's too much information to conveniently quote, so anyone who needs
the information leading to this response, please look at the original
post(s).
_____________

Your sample rate is *very* small compared to what FPGAs, ASICs,
processors, and CPLDs can handle.

You appear to 1) have a need for clock recovery which may be independent
per channel or may be the same clock for all channels, and 2) no
apparent way to discern which incoming bit is the first bit of a data frame.

Once you understand the nature of the incoming data, you can design a
mechanism to deal with it in a nice, compact fashion. If your target is
an FPGA, your experience may be better than in an ASIC since FPGAs have
shallow distributed memories. You should be able to assemble a
time-multiplexed mechanism to deserialize all 12 data channels and
interface to one memory to store your 32 12-bit words (in your example).
If you can design one channel to process one channel at 1 MHz, it
shouldn't be too difficult to stretch that same design to process 32
channels at an aggregate 32 MHz. Because your data speeds are slow, you
have a great ability to accomplish what you need in one tight module.

First concentrate on extracting the 12-bit data from one channel.
Understand what you need to get each data word into your system without
alignment problems. Once you have that issue licked, you can
investigate replicating that module 32 times (with a 32-wide MUX to
write several words to the memory on one incoming data bit cycle) or
time-multiplexing the module to interface cleanly to one memory.

To understand what you can accomplish with time-multiplexed processing,
take a look at the Xilinx Xcell article when they were touting "3D
processing" (their buzz word at the time for time-multiplexed operations).

pdf:
http://tinyurl.com/2qq2uz
-or-
http://www.xilinx.com/publications/xcellonline/xcell_47/xc_pdf/xc_3d47.pdf

or if you prefer html, the original 2-part TechXclusives article starts
here:

http://tinyurl.com/3dxnzf
-or-
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=-1209667&sGlobalNavPick=SUPPORT&sSecondaryNavPick=&multPartNum=1&sTechX_ID=kc_perf_time&languageID=1


I've designed several time-multiplexed systems to process multiple
independent channels. Where a feedback register is needed in a 1x
design, a single-port asynchronous-read memory (or dual-port synchronous
read) would be substituted in its place. Where a flow-through register
is used for a data pipeline, the same register can be used. The
technique is powerful an avoids duplicating the same function 32 times
in a low speed application. If you're stepping through the multiple
channels in the same order, you can also use fixed-length shift
registers instead of classical memories to make to flow... flow better.