Stream-in with XStream (IC-OA 6.1.3): how to replace bit sel

[Thomas Popp]

Hi,

I recently switched from IC-CDB 5.1.41 to IC-OA 6.1.3. As a matter of
fact, the stream-in/out tool PIPO has been replaced by XStream. The
transition went smoothly except for one thing:

For PIPO, the option "replaceBusBitChar" could be set to "true" in the
template file. This had the effect that signal names like mysignal[12]
were translated to mysignal<12> during stream-in and vice versa during
stream-out. It seems that such a functionality is not available for
XStream. The original option is not even mentioned in the PIPO->XStream
adoption guide and there is no further information available on the
Cadence support website.

Can anyone advise me on how to achieve such a translation with XStream?
I need it to match layouts (produced by XStream -> uses [x]) and
schematics (produced by VerilogIn -> uses <x&gt. I hope, it doesn't need
to be done manually.

Thanks,
-Thomas

 

[Andrew Beckett]

Thomas Popp wrote, on 02/17/10 14:43:

Hi,

I recently switched from IC-CDB 5.1.41 to IC-OA 6.1.3. As a matter of
fact, the stream-in/out tool PIPO has been replaced by XStream. The
transition went smoothly except for one thing:

For PIPO, the option "replaceBusBitChar" could be set to "true" in the
template file. This had the effect that signal names like mysignal[12]
were translated to mysignal<12> during stream-in and vice versa during
stream-out. It seems that such a functionality is not available for
XStream. The original option is not even mentioned in the PIPO->XStream
adoption guide and there is no further information available on the
Cadence support website.

Can anyone advise me on how to achieve such a translation with XStream?
I need it to match layouts (produced by XStream -> uses [x]) and
schematics (produced by VerilogIn -> uses<x&gt. I hope, it doesn't need
to be done manually.

Thanks,
-Thomas

On the Options form for File->Export/Import->Stream you can set (on the General
Tab) the "Text Namespace" to (say) Verilog.

Regards,

Andrew.

 

[Thomas Popp]

Am 19.02.2010 16:14, schrieb Andrew Beckett:

Thomas Popp wrote, on 02/17/10 14:43:

Hi,

I recently switched from IC-CDB 5.1.41 to IC-OA 6.1.3. As a matter of
fact, the stream-in/out tool PIPO has been replaced by XStream. The
transition went smoothly except for one thing:

For PIPO, the option "replaceBusBitChar" could be set to "true" in the
template file. This had the effect that signal names like mysignal[12]
were translated to mysignal<12> during stream-in and vice versa during
stream-out. It seems that such a functionality is not available for
XStream. The original option is not even mentioned in the PIPO->XStream
adoption guide and there is no further information available on the
Cadence support website.

Can anyone advise me on how to achieve such a translation with XStream?
I need it to match layouts (produced by XStream -> uses [x]) and
schematics (produced by VerilogIn -> uses<x&gt. I hope, it doesn't need
to be done manually.

Thanks,
-Thomas

On the Options form for File->Export/Import->Stream you can set (on the
General Tab) the "Text Namespace" to (say) Verilog.

Regards,

Andrew.

Hi Andrew,

Thanks a lot, that was exactly the option I was looking for. It works
fine now.

-Thomas