Stratix FPGA configuration issues

[Vadim Bishtein]

I am having trouble downloading my own VHDL code onto the
Stratix device through ByteBlaster. The device is housed on the
NIOS Board-Stratix Edition from Altera. Download process goes
normally, but when it is finished the on-board MAX CPLD loads
the Stratix with the default NIOS code from the FLASH. In the manual
Altera says that Stratix will be configured to the VHDL code if it is
programmed
through ByteBlaster cable. It doesn't work !

Anyone has any ideas ???

(the Stratix device is EP1S10 ES)

Even Altera support had no clue....

thanks,

 

[Leon Heller]

"Vadim Bishtein" <vbishtei@hotmail.com> wrote in message
news:c6oqqj$gc6$1@driftwood.ccs.carleton.ca...

I am having trouble downloading my own VHDL code onto the
Stratix device through ByteBlaster. The device is housed on the
NIOS Board-Stratix Edition from Altera. Download process goes
normally, but when it is finished the on-board MAX CPLD loads
the Stratix with the default NIOS code from the FLASH. In the manual
Altera says that Stratix will be configured to the VHDL code if it is
programmed
through ByteBlaster cable. It doesn't work !

Anyone has any ideas ???

(the Stratix device is EP1S10 ES)

Even Altera support had no clue....

Posting to comp.arch.fpga would be better for this.

Leon
--
Leon Heller, G1HSM
http://www.geocities.com/leon_heller

 

[Petter Gustad]

"Vadim Bishtein" <vbishtei@hotmail.com> writes:

I am having trouble downloading my own VHDL code onto the
Stratix device through ByteBlaster. The device is housed on the
NIOS Board-Stratix Edition from Altera. Download process goes
normally, but when it is finished the on-board MAX CPLD loads
the Stratix with the default NIOS code from the FLASH. In the manual
Altera says that Stratix will be configured to the VHDL code if it is
programmed
through ByteBlaster cable. It doesn't work !

Anyone has any ideas ???

(the Stratix device is EP1S10 ES)

Even Altera support had no clue....

What does your VHDL design do? You have to make sure that you at least
drive reconf_req (pin U2) high. Otherwise it might request a
reconfiguration right away and run the default design (web server)
from the flash.

Followup sat to comp.arch.fpga

Petter

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