Stratix 2 ALUT architecture patented ?

[lenz]

Hi,

is the new ALUT architecture of stratix 2 patented ?
I have looked at the US patent office but could not
find such a patent.

Thank you for your help.

 

[Austin Lesea]

Lenz,

I am sure that they have filed for their patents. Since it takes two or
more years, we will just have to wait and see what it is that gets patented.

How this is any different than f5/f6/f7/f8 muxes is also at issue: have
they just "renamed" an already existing architecture? Do they now
achieve the same packing that is already enjoyed by others?

Austin

 

[Michael]

Austin,

As a general rule, Altera likes to avoid using this site as a
marketing tool. Instead, we choose to focus just on relevant technical
questions. However, since you brought it up, the question at hand: is
the innovation in Stratix II just a renaming of the f5/f6/f7/f8 muxes
in Virtex products?

On the contrary, the Stratix II architecture represents a complete
redesign of a programmable logic fabric.

Recognizing the need for a more powerful and efficient approach than
the 4LUT + register fabric that all mainstream FPGAs have relied on
for years, Altera increased the capability and flexibility of the
Stratix II logic with a larger and truly adaptive logic module (ALM).
An ALM can efficiently implement one to two 6LUTs, any 5LUT and 3LUT
combination, two 5LUTs (for almost any 2 functions), any two 4LUTs
etc...all in a single logic block. (For more complete listing, look
here: http://www.altera.com/products/devices/stratix2/features/architecture/st2-lut.html)
Previous FPGA architectures have only had 4LUT capabilities without
routing between multiple logic blocks.

Virtex devices are really a 4LUT architecture with some MUXes (note
that "variable LUT terminology" was only recently mentioned in a white
paper but is not found in the data sheet). The f5/fX muxes are one way
to emulate larger LUT functions, but this approach comes at the cost
of multiple LC resources, routing structures between those LC's, and
requires that the synthesis tool (or the designer) intelligently map
to those muxes. Analysis of synthesis and place and route results,
suggests the f5/fX resources are commonly used in large distributed
memory functions and wide muxes, but rarely benefit wide LUT
functions.

Comparing results of how real designs synthesize and map to Stratix II
ALMs vs. Virtex-II Pro slices (the most direct comparison since each
ALM/slice is capable of 2 4LUT functions) shows a 54% efficiency
advantage for Stratix II. This increased logic efficiency also
results in better performance and lower power, since with more logic
density inside each logic block, less routing circuitry is used which
tends to be slower and leakier by comparison.

For those of you curious to find out more details on this, the
following white paper and web seminar may interest you:.

Logic Structure Comparison Between Stratix & Virtex-Based
Architectures
http://www.altera.com/literature/wp/wpstxiixlnx.pdf

http://www.altera.com/education/net_seminars/current/stratix2/ns-stratix2.html?f=sx2hp&k=g2

Mike Rather
Altera Corp.

Austin Lesea <austin@xilinx.com> wrote in message news:<c1gfrh$l613@cliff.xsj.xilinx.com>...

Lenz,

I am sure that they have filed for their patents. Since it takes two or
more years, we will just have to wait and see what it is that gets patented.

How this is any different than f5/f6/f7/f8 muxes is also at issue: have
they just "renamed" an already existing architecture? Do they now
achieve the same packing that is already enjoyed by others?

Austin

 

[Jim Granville]

Michael,
Since you popped your head over the parapet...

What's the story on MAX II Devices ?. There was glossary, timing
and lib files gradually appearing, and suddenly the Altera
web is cleansed and it's like MAX II is now 'off the radar' ?.
Would seem to indicate some problems.....

-jg

 

[austin]

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[Kenneth Land]

Austin,

I agree that performance claims will have to wait, but Jesse Kempa posted
the LE results for a Nios softcore on Stratix I vs. II. The numbers showed
just north of 30% fewer LE's used.

Perhaps you (or someone else) could get your hands on an early version of
Quartus II v4 and build some of your own designs and see for yourself. I'm
sure everyone here would be interested in the results. Maybe someone from
Altera would be willing to do it for you.

It would be best for someone to use real world designs that they already
have ported to both X and A.

Ken

"austin" <austin@xilinx.com> wrote in message
news:c1jt6i$72u1@cliff.xsj.xilinx.com...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[Austin Lesea]

Kenneth,

We noted that, and it is probably absolutely true. That would yield the
same results that we already achieve with our present architecture
because a 30% improvement is what is expected (and delivered) by the
Virtex LUTs and mux wiring.

I grant that they have now achieved parity in LUT usage with our two
year old product. They have even improved its speed performance over
their St1 by quite a bit, too.

Good news for Altera customers.

Austin

Kenneth Land wrote:

Austin,

I agree that performance claims will have to wait, but Jesse Kempa posted
the LE results for a Nios softcore on Stratix I vs. II. The numbers showed
just north of 30% fewer LE's used.

Perhaps you (or someone else) could get your hands on an early version of
Quartus II v4 and build some of your own designs and see for yourself. I'm
sure everyone here would be interested in the results. Maybe someone from
Altera would be willing to do it for you.

It would be best for someone to use real world designs that they already
have ported to both X and A.

Ken

"austin" <austin@xilinx.com> wrote in message
news:c1jt6i$72u1@cliff.xsj.xilinx.com...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[Luanne]

Jim Granville <no.spam@designtools.co.nz> wrote in message news:<T9d%b.28459$ws.3202154@news02.tsnz.net>...

Michael,
Since you popped your head over the parapet...

What's the story on MAX II Devices ?. There was glossary, timing
and lib files gradually appearing, and suddenly the Altera
web is cleansed and it's like MAX II is now 'off the radar' ?.
Would seem to indicate some problems.....

-jg

Hi Jim:

Rest assured there are no problems. The www.altera.com site was
refreshed; what you are experiencing is "housecleaning" on the site.
MAX II data, lib files and documentation will be posted on altera.com
when the product is launched - stay tuned.

Luanne Schirrmeister
-Altera

 

[Peter Alfke]

Memories of PREP, theidealistic but futile attempt at standardized benchmarks...
I really do not like the marketing twist that this thread is taking.

Xilinx had extra muxes for many years, Altera counters with more LUT
bits, Xilinx explains that Altera shares LUT inputs and has congested
routing,... and the spin goes on.
In reality its a synthesis and routing software issue.

I bet Altera can cook up an application where their LUTs look terrific,
and Xilinx can conjure an application where the limited access just
chokes the Altera LUTs. And who would be wiser ?

Don't expect "gentleman-like" behavior from marketing, the stakes are
too high.
But let's at least keep this newsgroup somewhat gentleman-like...
Peter Alfke
==============
Kenneth Land wrote:

Austin,

I agree that performance claims will have to wait, but Jesse Kempa posted
the LE results for a Nios softcore on Stratix I vs. II. The numbers showed
just north of 30% fewer LE's used.

Perhaps you (or someone else) could get your hands on an early version of
Quartus II v4 and build some of your own designs and see for yourself. I'm
sure everyone here would be interested in the results. Maybe someone from
Altera would be willing to do it for you.

It would be best for someone to use real world designs that they already
have ported to both X and A.

Ken

"austin" <austin@xilinx.com> wrote in message
news:c1jt6i$72u1@cliff.xsj.xilinx.com...
Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[Nicholas C. Weaver]

In article <103s244a4ugb899@news.supernews.com>,
Kenneth Land <kland1@neuralog1.com1> wrote:

Austin,

I agree that performance claims will have to wait, but Jesse Kempa posted
the LE results for a Nios softcore on Stratix I vs. II. The numbers showed
just north of 30% fewer LE's used.

Considering the impressive design mapping required in the NIOS 2 (the
FPGA talk on the subject was VERY-cool), how much redesign was
done/needed for Stratix II? Or is this Nios 1.1?
--
Nicholas C. Weaver nweaver@cs.berkeley.edu

 

[Kenneth Land]

Hi Peter,

I was suggesting that the engineers on this group *bypass* the marketing
groups of A and X and post how *their* designs map between the new choices.

Or are the people in this thread the marketing people you're warning us
about. I'm too new to know better. I know (of) you and that you're with X,
but not the others.

Sure someone could intentionally mislead, but I'd at least like to know how
some typical fpga group reader's design(s) mapped onto the latest offerings.

I know you could trust my designs, because I don't know enough to tweak them
for X or A. I'll bet there are many others who don't tweak designs to that
level either. (probably for better reasons

Ken


"Peter Alfke" <peter@xilinx.com> wrote in message
news:403E2BA6.AE630B1F@xilinx.com...

Memories of PREP, theidealistic but futile attempt at standardized
benchmarks...
I really do not like the marketing twist that this thread is taking.

Xilinx had extra muxes for many years, Altera counters with more LUT
bits, Xilinx explains that Altera shares LUT inputs and has congested
routing,... and the spin goes on.
In reality its a synthesis and routing software issue.

I bet Altera can cook up an application where their LUTs look terrific,
and Xilinx can conjure an application where the limited access just
chokes the Altera LUTs. And who would be wiser ?

Don't expect "gentleman-like" behavior from marketing, the stakes are
too high.
But let's at least keep this newsgroup somewhat gentleman-like...
Peter Alfke
==============
Kenneth Land wrote:

Austin,

I agree that performance claims will have to wait, but Jesse Kempa
posted
the LE results for a Nios softcore on Stratix I vs. II. The numbers
showed
just north of 30% fewer LE's used.

Perhaps you (or someone else) could get your hands on an early version
of
Quartus II v4 and build some of your own designs and see for yourself.
I'm
sure everyone here would be interested in the results. Maybe someone
from
Altera would be willing to do it for you.

It would be best for someone to use real world designs that they already
have ported to both X and A.

Ken

"austin" <austin@xilinx.com> wrote in message
news:c1jt6i$72u1@cliff.xsj.xilinx.com...
Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy
it,
I will forego any claims of performance, and just ask about
architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if
it
was actually designed this way then that is simply what it is. A true
6
LUT has 64 memory cells and the associated logic, and two of these
seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a
6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative
new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[google_guy]

austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of.

I can understand why. The way that Xilinx twists facts in their data
sheets would certainly lead them to expect that of everyone. Just how
many LCs *do* your parts have???

For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

What kind of gobbledygook is that? Correct me if I am wrong, but your
V2 is the newest and fastest parts you have, right? Certanly you
can't tout the Spartan 3 since not many people have even seen them and
they are much slower than most people would have expected given a 90
nm process.

And exactly how do you get a 40% speed advantage over anything with
your software? Do you have benchmarks to back that up?

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

I don't follow this. Are you saying their approach is good or bad?
If you are saying it is good, then you are agreeing with them. If you
are saying it is bad, aren't you also saying it is just like yours? I
guess the patents will tell all.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Yes, and some of those are in a unmarked grave out behind your
facility, no? What was that company name... was it Plus Logic? How
about NeoCAD? What are the others... ?

 

[Austin Lesea]

Guy?

Comments below.


google_guy wrote:

austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of.


I can understand why. The way that Xilinx twists facts in their data
sheets would certainly lead them to expect that of everyone. Just how
many LCs *do* your parts have???
Easy, just look at how many LUTs there are in the data sheet. You can

inflate the naw numbers any way you like, as opposed to using our "rules."

For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.


What kind of gobbledygook is that? Correct me if I am wrong, but your
V2 is the newest and fastest parts you have, right? Certanly you
can't tout the Spartan 3 since not many people have even seen them and
they are much slower than most people would have expected given a 90
nm process.
V2Pro is the latest production avaliable offering in 130 nm.

And exactly how do you get a 40% speed advantage over anything with
your software?
By being more clever than we were one year ago.

Do you have benchmarks to back that up?
Yes. Contyact your FAE and they will be delighted to show you the
benchmarks of over 200 large actual customer designs that we have in our
tool test suite.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.


I don't follow this. Are you saying their approach is good or bad?
Neither. It just looked at first glance that they had some muxes (just

like we do). That they have a more direct LUT/MUX/LUT path which is
faster may be true, and that would be good.

If you are saying it is good, then you are agreeing with them.
Hey, what is wrong with that? Yes, it is good.

If you

are saying it is bad, aren't you also saying it is just like yours? I
guess the patents will tell all.



Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.


Yes, and some of those are in a unmarked grave out behind your
facility, no?
Yes.

What was that company name... was it Plus Logic? How

about NeoCAD? What are the others... ?
I will let you tell us.

 

[Michael]

Austin,

Our data contradicts the performance claims you are making, but this
is not the right forum to argue back and forth about it.

Let's let the engineers and the market decide which claims to be leary
of.

Best Regards,
Mike


austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of. For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.

Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.

Austin

 

[Austin Lesea]

Michael,

True. All I pointed out is that the ALM architecture is a clear
improvement (for Altera) and (if) it also has speed benefits, then that
is even better.

A clear case of agreement.

I also mentioned that I don't believe your claims, and even if I did, we
now claim a 40% improvement.

You don't believe my claim, so we are even again. Scarey if we agree
too much....

So, here is the challenge: anyone who can actually do a design in both,
and then let us know how well it behaves? Of course, no one is likely
to believe just one design (as Peter notes), so the more who submit, the
merrier (and the more believable it would be).

I would only leave as a last note that this is a comparison of the
Virtex II Pro (two years old 0.13u) with the St2 (90 nm which isn't even
sampling yet).

Austin

 

[Peter Alfke]

google_guy wrote:

Yes, and some of those are in a unmarked grave out behind your
facility, no? What was that company name... was it Plus Logic? How
about NeoCAD? What are the others... ?

I don't like the nasty tone by that anonymous coward "google_guy" .
But regarding the graves that Austin referred to, they are from:
Intel, Motorola, Texas Instrument, AMD, Lucent, National Semi, and lots
of lesser players.

Let's stop the bickering and concentrate on the fascinating technical
possibilities offered by the new crops of FPGAs. Leave the mudslinging
to the marketing folks. They are better trained in it, and they can tell
the wildest stories with a straight face, without blushing. Let us be
engineers.
Peter Alfke

 

[Mikeandmax]

Peter writes

But regarding the graves that Austin referred to, they are from:
.............. AMD, Lucent,..........

Quote from Mark Twain follows:

"Rumors of my untimely demise have been greatly exaggerated."

might not be exact, but you get what I mean.

This is a terrific newsgroup. I know I have learned a fair amount about the
topic while perusing the posts.

But let's remember, AMD's PLD business isn't dead, nor is Lucent's - although
they BOTH now say LATTICE on the package. ;-)

Michael Thomas
LSC SFAE
New York/New Jersey
631-874-4968 fax 631-874-4977
michael.thomas@latticesemi.com
for the latest info on Lattice products - http://www.latticesemi.com
LATTICE - BRINGING THE BEST TOGETHER

 

[google_guy]

Austin Lesea <austin@xilinx.com> wrote in message news:<c1ligf$7oc2@cliff.xsj.xilinx.com>...

google_guy wrote:
austin <austin@xilinx.com> wrote in message news:<c1jt6i$72u1@cliff.xsj.xilinx.com>...

Michael,

Thank you very much. I have read all of the publicly available
materials, and am still puzzled by the claims.

Any claims of remarkable efficiency, you may understand, I am quite
leary of.


I can understand why. The way that Xilinx twists facts in their data
sheets would certainly lead them to expect that of everyone. Just how
many LCs *do* your parts have???
Easy, just look at how many LUTs there are in the data sheet. You can
inflate the naw numbers any way you like, as opposed to using our "rules."

How about Xilinx actually publishes the *real* numbers? If you
inflate the numbers, of course you would expect your competition to
inflate their numbers.

For example, if the claim of a St2 50% speed improvement is
really true, then our demonstrated 40% speed improvement on average in
the i6.2 release makes St2 only 10% faster than our 2 year old V2
Pro.....lowest speed grade. So leaving marketing to those who enjoy it,
I will forego any claims of performance, and just ask about architecture.


What kind of gobbledygook is that? Correct me if I am wrong, but your
V2 is the newest and fastest parts you have, right? Certanly you
can't tout the Spartan 3 since not many people have even seen them and
they are much slower than most people would have expected given a 90
nm process.
V2Pro is the latest production avaliable offering in 130 nm.

So what would you have Altera compare their products to, your V3 chips
that you won't have out next year?

And exactly how do you get a 40% speed advantage over anything with
your software?
By being more clever than we were one year ago.
Do you have benchmarks to back that up?
Yes. Contyact your FAE and they will be delighted to show you the
benchmarks of over 200 large actual customer designs that we have in our
tool test suite.

So your chips are not any faster, you have just figured out how to get
the speed out of your chips. If you want to compare software do that,
but we are talking about the chips, aren't we?

I was unclear on just how a ALM is any different from drawing the box
differently around the components. I am still puzzled, but the block
diagrams appears to have 3, 4, 5 and 6 LUTS with muxes, and maybe if it
was actually designed this way then that is simply what it is. A true 6
LUT has 64 memory cells and the associated logic, and two of these seems
a bit excessive and would not require any other logic or muxes at all.
Combining existing 4 LUTs to deliver some of the possible terms of a 6
LUT is a completely different matter.


I don't follow this. Are you saying their approach is good or bad?
Neither. It just looked at first glance that they had some muxes (just
like we do). That they have a more direct LUT/MUX/LUT path which is
faster may be true, and that would be good.

So you don't understand what they are doing, but you had to open your
mouth anyway.

If you are saying it is good, then you are agreeing with them.
Hey, what is wrong with that? Yes, it is good.
If you
are saying it is bad, aren't you also saying it is just like yours? I
guess the patents will tell all.



Regardless, it is enjoyable to hear about any radical or innovative new
architecture, as there are so many that now dot the landscape as dead
skeletons of past FPGAs.


Yes, and some of those are in a unmarked grave out behind your
facility, no?
Yes.
What was that company name... was it Plus Logic? How
about NeoCAD? What are the others... ?
I will let you tell us.

Hey, it's your graveyard.

 

[Ray Andraka]

I could make either family come out miles ahead of the other for a particular
design. The fact is, if you design to the part you'll get the best performance
from that part, but it will likely not port well to a dissimilar part. In my
cursory look at the new Altera architecture, I see structure there to support
wider functions, which is great for the naive user. It makes the synthesis job
a little harder since there are now even more ways to skin the cat. For heavily
pipelined designs, it generally isn't going to matter a whole lot if you've
already done the designs with 4-LUTs in mind. I'm not sure yet what it does to
the arithmetic functions. Altera had previously been a little weaker than
xilinx for arithmetic just because of the structure of the LEs and LAB when used
in arithmetic mode, and in the families prior to stratix there were row routing
congestion problems if you put a lot of arithmetic in one row. For typical
designs, either will do fine. Select on the feel-good parameters instead:
things like best comfort with tools, best price, best relationship with vendor,
best give-aways at trade shows. If your application is pushing the
envelope,however, you'll want to carefully evaluate each architecture to
determine which is going to best fit your design, and then design to that
architecture.

Kenneth Land wrote:

Hi Peter,

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759

 

[Ray Andraka]

If someone will pay for my time doing it (and be willing to fit in my
schedule), I'd be happy to do an app or two targeted to each of the
families, pulling out all the stops for each one to see which does better
for that app after all the tricks in my bag are applied. I'll guarantee the
internals of the two functionally equivalent designs would be rather
different. Of course that would only be a valid comparison for the pieces
of that application.

Austin Lesea wrote:

Michael,

True. All I pointed out is that the ALM architecture is a clear
improvement (for Altera) and (if) it also has speed benefits, then that
is even better.

A clear case of agreement.

I also mentioned that I don't believe your claims, and even if I did, we
now claim a 40% improvement.

You don't believe my claim, so we are even again. Scarey if we agree
too much....

So, here is the challenge: anyone who can actually do a design in both,
and then let us know how well it behaves? Of course, no one is likely
to believe just one design (as Peter notes), so the more who submit, the
merrier (and the more believable it would be).

I would only leave as a last note that this is a comparison of the
Virtex II Pro (two years old 0.13u) with the St2 (90 nm which isn't even
sampling yet).

Austin

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759