Strange simualtion result with #0

I am unable to understand the simulation result of the following code:

initial
begin
#1 a = 0;
#0 a = a + 1;
end

After the first statement, a = 0 at time 1 as expected. But on
executing the second, a is shown transitioning from x to 1. Shouldn't
it have been from 0 to 1 instead?
Could someone please explain this result?

Thanks

 

[Jonathan Bromley]

On Thu, 26 Mar 2009 01:01:12 -0700 (PDT), scr.forums@gmail.com wrote:

I am unable to understand the simulation result of the following code:

initial
begin
#1 a = 0;
#0 a = a + 1;
end

After the first statement, a = 0 at time 1 as expected. But on
executing the second, a is shown transitioning from x to 1. Shouldn't
it have been from 0 to 1 instead?

Yes, but the problem may be to do with how you
chose to observe this change.

If you use a waveform viewer, it may show you that a==1 immediately
after time 1, but a==x immediately before time 1; so the TOTAL
effect of the transition at time 1 is x->1. Indeed, if you were
to observe signal 'a' from any other initial or always block,
that's probably what you would see.

What makes you think you had an x->1 transition?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

On Mar 26, 1:49 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Thu, 26 Mar 2009 01:01:12 -0700 (PDT), scr.for...@gmail.com wrote:
I am unable to understand the simulation result of the following code:

initial
begin
#1 a = 0;
#0 a = a + 1;
end

After the first statement, a = 0 at time 1 as expected. But on
executing the second, a is shown transitioning from x to 1. Shouldn't
it have been from 0 to 1 instead?

Yes, but the problem may be to do with how you
chose to observe this change.

If you use a waveform viewer, it may show you that a==1 immediately
after time 1, but a==x immediately before time 1; so the TOTAL
effect of the transition at time 1 is x->1. Indeed, if you were
to observe signal 'a' from any other initial or always block,
that's probably what you would see.

What makes you think you had an x->1 transition?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Thanks for your reply. Yeah, i got it now. Had overlooked what you
stated now.