Strange problem with very simple state machine

[Roger Dahl]

Dear group,

I'm teaching myself VHDL and to that end, I got a prototype board with
a Xilinx Spartan 2 and WebPack 6.3.02 plus service packs.

I was working on a small design when I started having some strange
problems with a state machine. To locate the problem, I separated out
the state machine and simplified it as much as I could while still
retaining the problem. So I now have a complete design with an
extremely simple state machine that exhibits the problem, but I still
can't see that I made any mistakes. I've included that design in VHDL
below.

The state machine has two states. The first state sets a signal to 0,
and the second state inverts the signal. From everything I've read
about state machines and processes, the signal should turn to 1 when
the state machine goes to the second state and stay at 1 until the
state machine goes back to the first state. Instead, what happens is
that while the state machine is in the second state, the signal keeps
inverting as quickly as the chip can manage.

When I view the RTL schematic for the design, it is apparent why this
happens. While the state machine is in the second state, the signal is
simply run in a loop through a NOT gate.

I would much appreciate it if someone that knows more about VHDL than
I could take a look at the code below and see if I have missed
something fundamental about VHDL or state machines, or if this is a
bug in the Xilinx tools.

Thank you for any help!

Roger Dahl

--

library ieee;
use ieee.std_logic_1164.all;

entity sigtest is
port (
mclk : in std_logic;
d: out std_logic
);
end sigtest;

architecture behavioral of sigtest is

type state is (
write_a,
write_b
);

signal d_ctl : std_logic := '0';

signal cur_st : state := write_a;
signal next_st : state := write_b;

begin

d <= d_ctl;

process (mclk)
begin
if rising_edge(mclk) then
cur_st <= next_st;
end if;
end process;

process (cur_st)
begin
case cur_st is
when write_a =>
d_ctl <= '0';
next_st <= write_b;

when write_b =>
d_ctl <= not d_ctl;
next_st <= write_a;
end case;
end process;

end behavioral;