Strange FPGA problem

W

williams

Guest
Hello,

I am integrating an IP core and i am facing a strange problem.
One of the register of the IP core which is R/W register is not
writable ..in simulation I am able to write but when ported to FPGA I
am not able to write…its default value is also wrong and when I write
to one fixed register in that core... its value gets reflects on that
register. Reset value of all the register is ok and I am able to read
and write all R/W registers except one. What may be the
problem…..since simulation results shows that the IP is ok…so I cannot
pin point that tell the IP vendor that there is a bug in ur IP…..

Any feedback???
Thanks and Regards
Williams
 
Just a hunch, but this smells like a bitstream loading problem.
Perhaps your connection while loading the bitstream was not
OK. Try reloading the bitstream and check after that.

- Swapnajit.
--
SystemVerilog, DPI, Verilog PLI and all other good stuffs.
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