Guest
Hey everyone,
I cant figure out why this happens. I make some assignments and they
shud each trigger an always block. Thing is tho, they trigger the
always blocks in the exact reverse order of what i think shud happen.
Anyone got any ideas?
module top;
reg sig1, sig2, sig3, sig4;
initial
begin
sig1 = 0;
sig2 = 0;
sig3 = 0;
sig4 = 0;
end
always@(sig1)
$display($time, " sig1 %b", sig1);
always@(sig2)
$display($time, " sig2 %b", sig2);
always@(sig3)
$display($time, " sig3 %b", sig3);
always@(sig4)
$display($time, " sig4 %b", sig4);
endmodule
EXECUTION
# 0 sig4 0
# 0 sig3 0
# 0 sig2 0
# 0 sig1 0
Shudnt they be in the reverse order as in sig1 first, then sig2 etc....
I cant figure out why this happens. I make some assignments and they
shud each trigger an always block. Thing is tho, they trigger the
always blocks in the exact reverse order of what i think shud happen.
Anyone got any ideas?
module top;
reg sig1, sig2, sig3, sig4;
initial
begin
sig1 = 0;
sig2 = 0;
sig3 = 0;
sig4 = 0;
end
always@(sig1)
$display($time, " sig1 %b", sig1);
always@(sig2)
$display($time, " sig2 %b", sig2);
always@(sig3)
$display($time, " sig3 %b", sig3);
always@(sig4)
$display($time, " sig4 %b", sig4);
endmodule
EXECUTION
# 0 sig4 0
# 0 sig3 0
# 0 sig2 0
# 0 sig1 0
Shudnt they be in the reverse order as in sig1 first, then sig2 etc....