strange error

[gilbert]

Hi,

i have wrote a VHDL code as below.
i use Xilinx foundation platform.
The situation is:

syntax check --> Check Successful
Synthesis --> Error: HDL translation aborted. (HDL-105)

Is there anybody can help me ?

The problem confuse me for long time.

Thanks, Gilbert



-- begin my code
library IEEE;
use IEEE.std_logic_1164.all;
entity Buff is
port (
Data_in: in STD_LOGIC_VECTOR (3 downto 0 );
Data_flag: in STD_LOGIC;
Reset: in STD_LOGIC;
Addr: in STD_LOGIC_VECTOR(7 downto 0);
We: in STD_LOGIC;
data_out: out STD_LOGIC_VECTOR(3 downto 0)
);
end Buff;

architecture Buff_arch of Buff is
begin
process (Data_flag )
begin
if Reset= '1' then
elsif Rising_Edge(Data_flag) then
if We='1' then
case data_in(3 downto 0) is
when "1000" =>
data_out <= "1111";
when others=>
data_out <= "1111";
end case;
end if;
end if;
if We='0' then
case Addr(3 downto 0) is
when "0001" =>
data_out <= "ZZZZ";
when others =>
data_out <= "1111";
end case;
end if;

end process;
end Buff_arch;

-- end my code