strange compiler message

[Rob Granger]

Hi

I have just written a simple mux module, which selects one of 4 signals.
So I have a 2 bit select signal. But strangely the compiler gives me the
following message:

# ** Error: mux.vhd(18): Case statement covers only 4 out of 81 cases.
# ** Error: mux.vhd(25): VHDL Compiler exiting
# C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.

Why 81 cases? I just have 4 different ones for the sel?

Thanks!

library ieee;
use ieee.std_logic_1164.all;

entity MUX is
port( I0 : in std_logic_vector(3 downto 0);
I1 : in std_logic_vector(3 downto 0);
I2 : in std_logic_vector(3 downto 0);
I3 : in std_logic_vector(3 downto 0);
sel : in std_logic_vector(1 downto 0);
dout: out std_logic_vector(3 downto 0)
);
end MUX;

architecture behave of MUX is
begin
process(I0, I1, I2, I3, sel)
begin
case sel is
when "00" => dout <= I0;
when "01" => dout <= I1;
when "10" => dout <= I2;
when "11" => dout <= I3;
end case;
end process;
end behave;

 

[Rob Granger]

Mike Treseler schrieb:

Rob Granger wrote:
Hi

I have just written a simple mux module, which selects one of 4 signals.
So I have a 2 bit select signal. But strangely the compiler gives me the
following message:

# ** Error: mux.vhd(18): Case statement covers only 4 out of 81 cases.
# ** Error: mux.vhd(25): VHDL Compiler exiting
# C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.

add a when others case:



when "01" => dout <= I1;
when "10" => dout <= I2;
when "11" => dout <= I3;
when others => dout <= I0;

Thanks Mike, I completley forgot all the possible combinatios with XZ
and so on that the input signal could have

 

[Mike Treseler]

Rob Granger wrote:

Hi

I have just written a simple mux module, which selects one of 4 signals.
So I have a 2 bit select signal. But strangely the compiler gives me the
following message:

# ** Error: mux.vhd(18): Case statement covers only 4 out of 81 cases.
# ** Error: mux.vhd(25): VHDL Compiler exiting
# C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.

add a when others case:



when "01" => dout <= I1;
when "10" => dout <= I2;
when "11" => dout <= I3;
when others => dout <= I0;

 

On Feb 24, 1:38 pm, Rob Granger <R...@hotmaiil.com> wrote:

Mike Treseler schrieb:



Rob Granger wrote:
Hi

I have just written a simple mux module, which selects one of 4 signals.
So I have a 2 bit select signal. But strangely the compiler gives me the
following message:

# ** Error: mux.vhd(18): Case statement covers only 4 out of 81 cases.
# ** Error: mux.vhd(25): VHDL Compiler exiting
# C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed.

add a when others case:

when "01" => dout <= I1;
when "10" => dout <= I2;
when "11" => dout <= I3;
when others => dout <= I0;

Thanks Mike, I completley forgot all the possible combinatios with XZ
and so on that the input signal could have

If your intent is purely to shut the compiler up so you can get
synthesised hardware, this is a good solution. If you want a more
robust simulation model which lets you back-trace errors better,
though, consider making your case statement a little more involved.
You might want behaviour so that any "X"'s in the sel force "X"'s in
the output. You might want to wrap the "sel" case in the function
'to_01x' so that using "H" or "L" as an input still does the right
thing, or even (depending on how you're using the multiplexer) allow a
sel value of "0X" to produce a non-X output when I0 and I1 are the
same, and "X" otherwise. You can wrap yourself in knots of you chose
to, but as a bare minimum, having "X in the input to leads to X in the
output" semantics are often useful.

- Kenn