strange behaviour of the design

[sameer]

hi geeks,

I have been using the xilinx foundation 5.2i and 4.2i. The design used
to work on board with both these versions earlier. But now with a few
additions to the code/design , the code some times works with 4.2i but
never with 5.2i.

I brought out (on the board) the internal signals ,but very strange
behaviour is seen, which is very absurd e.g. the signals required for
the state machine to go to the next state are generated, but the state
machine remains in the same state . Another example :- a signal has to
be set under certain conditions, this conditions are seen on the debug
pins, but still the signal is not set. Here there is no timing issue,
all the timigs are met .

I am really clue less as the synth/ warnings are also inconclusive. Is
it due to some fanout related issue (tool didnt issue any warning abt
it though..)

If anybody has faced similar problem ?

 

[Marc Guardiani]

Yes, I've had similar problems. Compiled a CPLD with 4.2 and it worked.
Didn't change a thing and compiled it with 5.x and it did not work.
IMHO, the 5.x tools are worthless.

sameer wrote:

hi geeks,

I have been using the xilinx foundation 5.2i and 4.2i. The design used
to work on board with both these versions earlier. But now with a few
additions to the code/design , the code some times works with 4.2i but
never with 5.2i.

I brought out (on the board) the internal signals ,but very strange
behaviour is seen, which is very absurd e.g. the signals required for
the state machine to go to the next state are generated, but the state
machine remains in the same state . Another example :- a signal has to
be set under certain conditions, this conditions are seen on the debug
pins, but still the signal is not set. Here there is no timing issue,
all the timigs are met .

I am really clue less as the synth/ warnings are also inconclusive. Is
it due to some fanout related issue (tool didnt issue any warning abt
it though..)

If anybody has faced similar problem ?

 

[Jim Granville]

sameer wrote:

hi geeks,

I have been using the xilinx foundation 5.2i and 4.2i. The design used
to work on board with both these versions earlier. But now with a few
additions to the code/design , the code some times works with 4.2i but
never with 5.2i.

Try the newest version of the SW ?
There have been reports of a back-step around 5.2, but I think ~V6.2 is
current.
-jg

 

[Andy Peters]

sameer.gandhi@wipro.com (sameer) wrote in message news:<f7e64c3a.0405231015.674ed9ee@posting.google.com>...

hi geeks,

I have been using the xilinx foundation 5.2i and 4.2i. The design used
to work on board with both these versions earlier. But now with a few
additions to the code/design , the code some times works with 4.2i but
never with 5.2i.

I brought out (on the board) the internal signals ,but very strange
behaviour is seen, which is very absurd e.g. the signals required for
the state machine to go to the next state are generated, but the state
machine remains in the same state . Another example :- a signal has to
be set under certain conditions, this conditions are seen on the debug
pins, but still the signal is not set. Here there is no timing issue,
all the timigs are met .

I am really clue less as the synth/ warnings are also inconclusive. Is
it due to some fanout related issue (tool didnt issue any warning abt
it though..)

If anybody has faced similar problem ?

Did you bother to simulate the design?

-a