Strange behavior with counter (decreases instead of increasi

[yhs2012]

Hello all. I have a very strange thing happening with my FPGA.

I have Xilinx Spartan-3E FPGA, that I am programming to count externa
pulses in 1us time bins. The way I'm doing that, is I have a pulse inde
counter, that increments whenever there's a rising edge on the puls
counter. (No resetting, no enabling, etc.) Then I have another loop tha
checks the count on the pulse counter every 1us, and writes the "puls
index" to an off-board SDRAM chip.

So I have an always block like this:

always @(posedge pulse_in) begin
pulse_index <= pulse_index + 1;
end

This works fine 99.9% of the time, but about 100-200 times out of
1,000,000 time bins, the "pulse index" decreases between consecutive tim
bins. For example, it could go from 195 to 194. This does not seem to b
related to the counter being full either (for example reaching 255 on
8-bit counter), because this happens with different counter sizes, and i
happens near the mid range of the counter value.

Anyone have any idea what might be happening? I suspect some sort o
hardware-related issue, e.g. the pulses I am inputting is not clea
enough.

Some facts:
1. The number of errors seem to be roughly proportional the input puls
rate. So if I send 2MHz instead of 1MHz, I get roughly twice the number o
errors.

2. The value of "pulse_index" does not go directly into the SDRAM. Th
value is written to a different register every 1us, which is written into
FIFO, which finally goes into the SDRAM.



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[BobH]

On 7/26/2012 11:09 AM, yhs2012 wrote:

Hello all. I have a very strange thing happening with my FPGA.

I have Xilinx Spartan-3E FPGA, that I am programming to count external
pulses in 1us time bins. The way I'm doing that, is I have a pulse index
counter, that increments whenever there's a rising edge on the pulse
counter. (No resetting, no enabling, etc.) Then I have another loop that
checks the count on the pulse counter every 1us, and writes the "pulse
index" to an off-board SDRAM chip.

So I have an always block like this:

always @(posedge pulse_in) begin
pulse_index <= pulse_index + 1;
end

This works fine 99.9% of the time, but about 100-200 times out of a
1,000,000 time bins, the "pulse index" decreases between consecutive time
bins. For example, it could go from 195 to 194. This does not seem to be
related to the counter being full either (for example reaching 255 on a
8-bit counter), because this happens with different counter sizes, and it
happens near the mid range of the counter value.

Anyone have any idea what might be happening? I suspect some sort of
hardware-related issue, e.g. the pulses I am inputting is not clean
enough.

Some facts:
1. The number of errors seem to be roughly proportional the input pulse
rate. So if I send 2MHz instead of 1MHz, I get roughly twice the number of
errors.

2. The value of "pulse_index" does not go directly into the SDRAM. The
value is written to a different register every 1us, which is written into a
FIFO, which finally goes into the SDRAM.

Is the input pulse that you are measuring synchronized to the clock that
you are using for the rest of the logic? If it is not synchronized, you
will get timing violations occasionally. Counters can behave
unpredictably with timing violations because different bits in the
counter may have different delays due to placement and routing
differences. Look up de-metastabilization for more info.

Good Luck,
BobH

 

[glen herrmannsfeldt]

yhs2012 <3610@embeddedrelated> wrote:

Hello all. I have a very strange thing happening with my FPGA.

I have Xilinx Spartan-3E FPGA, that I am programming to count external
pulses in 1us time bins. The way I'm doing that, is I have a pulse index
counter, that increments whenever there's a rising edge on the pulse
counter. (No resetting, no enabling, etc.) Then I have another loop that
checks the count on the pulse counter every 1us, and writes the "pulse
index" to an off-board SDRAM chip.

This problem is well known. The usual solution is to use a
gray-code counter.

The problem comes when you latch the value while it is changing,
and one changes (or has routing delay) different from the other.

Gray code only changes one bit on each count, such that you
always get one value or the next.

-- glen

 

[yhs2012]

Problem solved!

I used a gray counter and I am getting no errors so far.

Thanks so much for your help guys. You guys rock!

yhs2012 <3610@embeddedrelated> wrote:
Hello all. I have a very strange thing happening with my FPGA.

I have Xilinx Spartan-3E FPGA, that I am programming to count external
pulses in 1us time bins. The way I'm doing that, is I have a puls
index
counter, that increments whenever there's a rising edge on the pulse
counter. (No resetting, no enabling, etc.) Then I have another loo
that
checks the count on the pulse counter every 1us, and writes the "pulse
index" to an off-board SDRAM chip.

This problem is well known. The usual solution is to use a
gray-code counter.

The problem comes when you latch the value while it is changing,
and one changes (or has routing delay) different from the other.

Gray code only changes one bit on each count, such that you
always get one value or the next.

-- glen

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Posted through http://www.FPGARelated.com