Strange behavior when simulating with IO path delay

[cy]

Simulating this design in Modelsim would include io path delay of
100ns
before dataout signal change from "XX" -> "00".

This is strange because the IO path delay would only be included
when there is a valid posedge transition in clk port.
In this case, clk port value is always "Z"/"X" & the IO path delay
should not be included.
Is there any explanation regarding this situation?

module vdff(clk, dataout);
input clk;
output [1:0] dataout;
reg [1:0] dataout_tmp;

specify
(posedge clk => (dataout[0] +: dataout_tmp[0])) = (100, 100);
(posedge clk => (dataout[1] +: dataout_tmp[1])) = (100, 100);
endspecify

initial
begin
dataout_tmp = 2'b0;
end

assign dataout = dataout_tmp;
endmodule