strained Si cmos

J

jason

Guest
Hello All

Anyone knows the process flow of a strained Si cmos device?
The drain and source region is strained as well?
Kindly recommend any links or papers touch on the details of
fabrication

Thank you all


Jason
 
jason wrote:
Hello All

Anyone knows the process flow of a strained Si cmos device?
The drain and source region is strained as well?
Kindly recommend any links or papers touch on the details of
fabrication

Thank you all


Jason
Click to expand...
http://www.plsgoogleit.com/

And please do your homework yourself, looking at all your recent
post they sure all look like that ...



Sylvain
 
On Sun, 28 Aug 2005 11:38:58 +0200, Sylvain Munaut wrote:

jason wrote:
Hello All

Anyone knows the process flow of a strained Si cmos device?
The drain and source region is strained as well?
Kindly recommend any links or papers touch on the details of
fabrication

Thank you all


Jason


http://www.plsgoogleit.com/

And please do your homework yourself, looking at all your recent
post they sure all look like that ...
Click to expand...
Sometimes search engines are faster than even newsgroups. ;-)


--
Keith
 
I do not understand what you mean. I have searched and googled and
yahooed.
Just the article did not tell much about the fabrication steps. Just
the final cross sectional views
So I dropped a posting and hope someone may be able to give one or two
advice.
I am not asking anyone to tell me to regoogle
I hope you do not misunderstand me.
And I found that engineered substrate comes with the top layer with
strained Si layer, so I wonder if source and drain surface is strained
si or will be deposit some other epi layers.
I did do my google search. I just hope when people want to give advice,
please give it with a open heart and rational thinking.
It is not a homework too. It is something I wish to know through self
reading.
Thank you

Jason
 
By the way, before I sent out those enquiry , I have done many hours of
online search and IEEE search. No need for me to convince anyone. Just
whether someone wish to share opinion or not, he is to decide.
Cheers

Jason
 
On 28 Aug 2005 17:04:25 -0700, "jason" <cheanglong@gmail.com> wrote:

I do not understand what you mean. I have searched and googled and
yahooed.
Just the article did not tell much about the fabrication steps. Just
the final cross sectional views
So I dropped a posting and hope someone may be able to give one or two
advice.
I am not asking anyone to tell me to regoogle
I hope you do not misunderstand me.
And I found that engineered substrate comes with the top layer with
strained Si layer, so I wonder if source and drain surface is strained
si or will be deposit some other epi layers.
I did do my google search. I just hope when people want to give advice,
please give it with a open heart and rational thinking.
It is not a homework too. It is something I wish to know through self
reading.
Thank you

Jason
Click to expand...
Hey, Jason! Where do you work, or where do you go to school?

Food for thought... would straining a highly doped region do much, if
anything?

Conversely, how about a lightly doped invertible region (also known as
the channel :)

To acquire your engineering stripes you need to do a little
"what-iffing" on your own.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
On Sun, 28 Aug 2005 17:04:25 -0700, jason wrote:

I do not understand what you mean. I have searched and googled and
yahooed.
Click to expand...
I don't usually google, nor am I a yahoo, but search.com (searching
on the amazing string; "strained silicon") pulls this one up right up on
top (with a picture of the strained area and all):

http://www.research.ibm.com/resources/press/strainedsilicon/

I don't know *too* much about these things, but I do know how to use a
search engine.


Just the article did not tell much about the fabrication steps. Just the
final cross sectional views
So I dropped a posting and hope someone may be able to give one or two
advice.
Click to expand...
If you want to know about the fabrication steps, try a patent search.
Such things are often the subjects of gazillions of patents. You might
even try a search of http://www.research.ibm.com/. They've been known to
dabble in such things.

I am not asking anyone to tell me to regoogle I hope you do not
misunderstand me.
Click to expand...

I find a lot of what you ask with a ten-second search.

And I found that engineered substrate comes with the top layer with
strained Si layer, so I wonder if source and drain surface is strained
si or will be deposit some other epi layers. I did do my google search.
Click to expand...
Search some more! The pictures in the obvious links tell a story.

I just hope when people want to give advice, please give it with a open
heart and rational thinking. It is not a homework too. It is something I
wish to know through self reading.
Click to expand...
Trust me, what you're looking for *is* on-line, at least to the level
you're asking. Those who really know their stuff here may not want to
participate in the discussion, since much is proprietary. Web-searches
are your friend!

--
Keith
 
Thank you Keith
I found that page and was in pdf file few days back. I wonder if there
is sites that shows one step by one step in constructing a strained
cmos. For example, after halo implant, followed by heavy implant of
source drain and then ...
I will keep searching. Just that it has been few days search and did
not find it. I just hope if someone knows it and can share with me.
Thank you Keith.

Jason
 
Hi Jim

Thanks a lot for the food for thought.
I do not know if straining would help or lightly doped invertible
region would do better.
That's why I have to find out about it. So far, many sites shows
straining the Si will increase the mobility , therefore it is good
choice when scaling a cmos down to deep submicron.
As for a lightly doped invertible region, you mean the doped of boron
to n channel and phosphorous to p channel , is it?
If so, it is to smoothen the strong field as what I have read

I am going to school! :)
Any other advice, please tell me
Thank you all for writing back with positive and constructive
discussion
rather than critics that is not true!

Thank you all

Jason
 
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