Store serial data inside an array

K

Konx

Guest
Hi everyone.

I'm here again with another small problem ^_^

I want to design a module that performs a simple operation: store
synchronous serial data inside an array. This is my idea of the
design:

module gossipo_out(clk_40, data_array, token, data_ready_flag,
pixel_out);

input clk_40;
input pixel_out; //Serial data
input token;

output [47:0] data_array;
output data_ready_flag;

//Wire declaration
wire clk_40;
wire pixel_out;
wire token;

//Registered output
reg [47:0] data_array;
reg data_ready_flag;

//counter
reg [5:0] clk_counter;

//Cycle to fill the array.

always @ (posedge clk_40)
if(token)
begin
data_array[clk_counter] <= pixel_out;
clk_counter <= clk_counter + 6'd1;
end

always@(negedge token)
begin
data_ready_flag <= 1'b1; //This data is set to zero externally after
the read-out of the data_array
clk_counter <= 6'b000000;
end

endmodule



This solution is not working, because the clk_counter cannot be used
inside the data_array[clk_counter] (at least, the compiler gives me
problem with this signal so I suppose the problem is there. This is
the error for reference:

Multi-source in Unit <gossipo_out> on signal
<Mcount_clk_counter_cy<0>>; this signal is connected to multiple
drivers)

The "computer-programming oriented" solution would be to use a simple
integer variable to count, something like:

integer i;

always @ (posedge clk_40)
if(token)
begin
clk_counter <= clk_counter + 6'd1;
i = i+1;
end

always@(negedge token)
begin
data_ready_flag <= 1'b1;
i = 0;
end


This solution is actually "working" (to me, "working" means that the
synthesizer doesn't show any error).

Any hint about the correct solution (and most important: why is the
correct solution?).

Sorry for these basic questions (I need to take a verilog course, I
know :p).

Thanks in advance for any help

Francesco.
 
On 8 Nisan, 11:52, Konx <cesco...@gmail.com> wrote:
Hi everyone.

I'm here again with another small problem ^_^

I want to design a module that performs a simple operation: store
synchronous serial data inside an array. This is my idea of the
design:

module gossipo_out(clk_40, data_array, token, data_ready_flag,
pixel_out);

input clk_40;
input pixel_out; //Serial data
input token;

output [47:0] data_array;
output data_ready_flag;

//Wire declaration
wire clk_40;
wire pixel_out;
wire token;

//Registered output
reg [47:0] data_array;
reg data_ready_flag;

//counter
reg [5:0] clk_counter;

//Cycle to fill the array.

always @ (posedge clk_40)
if(token)
begin
  data_array[clk_counter] <= pixel_out;
  clk_counter <= clk_counter + 6'd1;
end

always@(negedge token)
begin
  data_ready_flag <= 1'b1; //This data is set to zero externally after
the read-out of the data_array
  clk_counter <= 6'b000000;
end

endmodule

This solution is not working, because the clk_counter cannot be used
inside the data_array[clk_counter] (at least, the compiler gives me
problem with this signal so I suppose the problem is there. This is
the error for reference:

Multi-source in Unit <gossipo_out> on signal
Mcount_clk_counter_cy<0>>; this signal is connected to multiple
drivers)

The "computer-programming oriented" solution would be to use a simple
integer variable to count, something like:

integer i;

always @ (posedge clk_40)
if(token)
begin
  clk_counter <= clk_counter + 6'd1;
  i = i+1;
end

always@(negedge token)
begin
data_ready_flag <= 1'b1;
i = 0;
end

This solution is actually "working" (to me, "working" means that the
synthesizer doesn't show any error).

Any hint about the correct solution (and most important: why is the
correct solution?).

Sorry for these basic questions (I need to take a verilog course, I
know :p).

Thanks in advance for any help

Francesco.
Click to expand...
As a newbie, my comment is that;
Every always block is a circuit and if you assign a value to same
variable in
two different always block, you connect the two output to same point.
So,
you are taking a multiple drivers error.

This solutin is acceptable(?)
always@(posedge clk_40)
if(token) begin
data_array[clk_counter] <= pixel_out;
clk_counter <= clk_counter + 6'd1;
end else begin
data_ready_flag <= 1'b1; //This data is set to zero externally
//after the read-out of the data_array
clk_counter <= 6'd0;
end

Sto.
 
On 8 Apr, 12:38, Stonerain <ali...@gmail.com> wrote:

As a newbie, my comment is that;
Every always block is a circuit and if you assign a value to same
variable in
two different always block, you connect the two output to same point.
So,
you are taking a multiple drivers error.
Click to expand...
ok, I understand this.

This solutin is acceptable(?)
always@(posedge clk_40)
 if(token) begin
   data_array[clk_counter] <= pixel_out;
   clk_counter <= clk_counter + 6'd1;
 end else begin
   data_ready_flag <= 1'b1;  //This data is set to zero externally
                             //after the read-out of the data_array
   clk_counter <= 6'd0;
 end
Click to expand...
The problem with this solution is that you set the data_ready_flag
every time you don't have a token. Instead I want to set the
data_ready_flag ONLY when the token goes down (maybe I could do in
another way: I set the data_ready_flag the following clk cycle after
the 48th clk cycle...I'll try this).

Thanks for the answer :)

Francesco.
 
On 8 Nisan, 15:00, Konx <cesco...@gmail.com> wrote:
On 8 Apr, 12:38, Stonerain <ali...@gmail.com> wrote:



As a newbie, my comment is that;
Every always block is a circuit and if you assign a value to same
variable in
two different always block, you connect the two output to same point.
So,
you are taking a multiple drivers error.

ok, I understand this.



This solutin is acceptable(?)
always@(posedge clk_40)
 if(token) begin
   data_array[clk_counter] <= pixel_out;
   clk_counter <= clk_counter + 6'd1;
 end else begin
   data_ready_flag <= 1'b1;  //This data is set to zero externally
                             //after the read-out of the data_array
   clk_counter <= 6'd0;
 end

The problem with this solution is  that you set the data_ready_flag
every time you don't have a token. Instead I want to set the
data_ready_flag ONLY when the token goes down (maybe I could do in
another way: I set the data_ready_flag the following clk cycle after
the 48th clk cycle...I'll try this).

Thanks for the answer :)

Francesco.
Click to expand...
Or maybe you should try


always@(posedge clk_40 or negedge token)
if(token) begin
data_array[clk_counter] <= pixel_out;
clk_counter <= clk_counter + 6'd1;
end else begin
data_ready_flag <= 1'b1; //This data is set to zero externally
//after the read-out of the data_array
clk_counter <= 6'd0;
end
 
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