J
JSreeniv
Guest
Hi all,
Could anyone give me the steps to verify the requirement given below
The count_pulses_for_period_pc0 is a register/counter that contains
the time period left to count the rising edges of the pulse_din0 pin
via Pulse Counter 0. This register is loadable and readable via the
processor. It is referred as CNT_P4P_PC0.
The CNT_P4P_PC0 starts and continue decrementing at a rate of 100ns
when the pulse_cnt_config (3:2) are set to 00, 1us when the
pulse_cnt_config (3:2) are set to 01 or 10us when the pulse_cnt_config
(3:2) are set to 1x and the following sequence of conditions occur.
a) The pulse_cnt_config (1:0) = 11.
b) The CNT_P4P_PC0 does not equal 0x0_0000.
c) A 1 is written to the pulse_cnt_ctrl register bit 0 (Start
measurement).
My Steps for this requirement:
--------------------------------------------
1. wait for 500 ns: output is dsp_d = 0x00000000 (this is processor
data bus)
2. active the power on reset signal(por_n = 0): dsp_d = 0
3. Read the current value in the PC_0 (pulse_counter_0_results
register/counter): READ(0x0B000) ; its reg address
4. Enable the bit 20 by setting up inhibit_1 register to start the
process: write(0x00011, 0x00000000)
5. configure the mode for time base by setting up using
pulse_cnt_config(3:2) to 00: WRITE(0x0B010, 0x00000000)
6. Configure the mode to measure the number of puless using
pulse_cnt_config(1:0) to 11: WRITE(0x0B010, 00000003)
7. load the time for counting on CNT_P4P_PC0 counter/reg, here i am
loading time 1 ms: WRITE(0x0B008, 0x0000003E8)
8.after 50 ns, i am toggling the pulse_din0 input signal with time
period 200 ns ( this is in confuse or doubt)
9. i am waiting for the same laodable time (1 ms) to check the
counting process is over from the status bit of register
pulse_counter_sts: READ(0x0B0110
10. from this step i am unable to make the process:
where from here i have to i have to find the number of count pulses,
and not getting how to show when CNT_P4P_PC0 decrements to 0, and PC_0
increment by 1
please some one give exposure on this issue...if need i will provide
required details.
Sreeni
Design Engineer
Could anyone give me the steps to verify the requirement given below
The count_pulses_for_period_pc0 is a register/counter that contains
the time period left to count the rising edges of the pulse_din0 pin
via Pulse Counter 0. This register is loadable and readable via the
processor. It is referred as CNT_P4P_PC0.
The CNT_P4P_PC0 starts and continue decrementing at a rate of 100ns
when the pulse_cnt_config (3:2) are set to 00, 1us when the
pulse_cnt_config (3:2) are set to 01 or 10us when the pulse_cnt_config
(3:2) are set to 1x and the following sequence of conditions occur.
a) The pulse_cnt_config (1:0) = 11.
b) The CNT_P4P_PC0 does not equal 0x0_0000.
c) A 1 is written to the pulse_cnt_ctrl register bit 0 (Start
measurement).
My Steps for this requirement:
--------------------------------------------
1. wait for 500 ns: output is dsp_d = 0x00000000 (this is processor
data bus)
2. active the power on reset signal(por_n = 0): dsp_d = 0
3. Read the current value in the PC_0 (pulse_counter_0_results
register/counter): READ(0x0B000) ; its reg address
4. Enable the bit 20 by setting up inhibit_1 register to start the
process: write(0x00011, 0x00000000)
5. configure the mode for time base by setting up using
pulse_cnt_config(3:2) to 00: WRITE(0x0B010, 0x00000000)
6. Configure the mode to measure the number of puless using
pulse_cnt_config(1:0) to 11: WRITE(0x0B010, 00000003)
7. load the time for counting on CNT_P4P_PC0 counter/reg, here i am
loading time 1 ms: WRITE(0x0B008, 0x0000003E8)
8.after 50 ns, i am toggling the pulse_din0 input signal with time
period 200 ns ( this is in confuse or doubt)
9. i am waiting for the same laodable time (1 ms) to check the
counting process is over from the status bit of register
pulse_counter_sts: READ(0x0B0110
10. from this step i am unable to make the process:
where from here i have to i have to find the number of count pulses,
and not getting how to show when CNT_P4P_PC0 decrements to 0, and PC_0
increment by 1
please some one give exposure on this issue...if need i will provide
required details.
Sreeni
Design Engineer