std_logic_vector vs unsigned

[Chuck McManis]

If I've got two signals in VHDL :
signal pwm_thresh : std_logic_vector (31 downto 0);
signal pwm_count : std_logic_vector (31 downto 0);

and I write ...
if ( pwm_thresh > pwm_count ) then
pwm <= '1';
else
pwm <= '0';
end if;

Does it work? I've not managed to successfully simulate it yet. Perhaps if I
wrote:
if ( unsigned(pwm_thresh) > unsigned(pwm_count) ) then


--
--Chuck McManis
Email to the devnull address is discarded
http://www.mcmanis.com/chuck/

 

[Martin Thompson]

"Chuck McManis" <devnull@mcmanis.com> writes:

If I've got two signals in VHDL :
signal pwm_thresh : std_logic_vector (31 downto 0);
signal pwm_count : std_logic_vector (31 downto 0);

Why not define these as "unsigned(31 downto 0)"? You're representing
real numbers after all, not just large collections of bits (which is
all a std_logic_vector implies).

and I write ...
if ( pwm_thresh > pwm_count ) then
pwm <= '1';
else
pwm <= '0';
end if;

Then that should work. Remember to include
use ieee.numeric_std.all;
at the top!

Then you don't need to faff about with type-casting.

HTH,
Martin

--
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt