std_logic_vector type port doesn't work after synthesis.

[Mike]

Hi

I encountered a problem during synthesis and I really hope
I can get your help.

I declared a std_logic_vector(7 downto 0) (inout type) entity port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port wouldn't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".

BTW, even I initialize this port to "ZZZZZZZZ"
in the entity definition, it still doesn't work.

Thanks a lot.

Mike

 

[Mike Treseler]

Mike wrote:

I declared a std_logic_vector(7 downto 0) (inout type) entity port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port wouldn't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".

Post your code. Your output enable logic is likely the problem.

-- Mike Treseler