'STD_LOGIC_VECTOR ' to 'unsigned' type casting

[Ben Nguyen]

Is there a built in function that can convert a STD_LOGIC_VECTOR type
to an 'unsigned' type?

(Im using Xilinx's ISE 4.1 SP3)

Thanks!

 

[Allan Herriman]

On 16 Sep 2003 20:07:04 -0700, benn686@hotmail.com (Ben Nguyen) wrote:

Is there a built in function that can convert a STD_LOGIC_VECTOR type
to an 'unsigned' type?

No, there are no "built in" functions that do that.
(BTW, std_logic_vector and unsigned aren't part of the the VHDL
language.)

but...

Yes, there are "standard" functions to do your conversion in the sense
that there are standard packages that add functionality you want to
the language: ieee.std_logic_1164 in the case of std_logic_vector, and
ieee.numeric_std in the case of unsigned and signed.

You will need to add the following lines to your VHDL source:

-- before your architecture
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

....

-- inside a declarative region in your architecture
signal un : unsigned(whatever downto 0);
signal slv : std_logic_vector(whatever downto 0);

....

-- now you can do conversions
un <= unsigned(slv);
slv <= std_logic_vector(un);

-- you can do arithmetic too
un <= un + 1;

-- this won't work (arith isn't (and shouldn't be) defined for slv)
slv <= slv + 1;


Note: some older tools don't support ieee.numeric_std. They probably
will support other (almost) equivalent packages such as
std_logic_unsigned.
Read the FAQ for details.

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector

(Im using Xilinx's ISE 4.1 SP3)

6.1 SP1 is available.

Regards,
Allan.

 

[jussi l]

take a look at e.g.
http://dz.ee.ethz.ch/support/ic/vhdl/vhdlsources.en.html

regards,
juza

"Ben Nguyen" <benn686@hotmail.com> wrote in message
news:e604be8.0309161907.504beb61@posting.google.com...

Is there a built in function that can convert a STD_LOGIC_VECTOR type
to an 'unsigned' type?

(Im using Xilinx's ISE 4.1 SP3)

Thanks!

 

[Egbert Molenkamp]

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:0urfmv0gj3ourln203h1f7pj1vet3or1v0@4ax.com...

Note: some older tools don't support ieee.numeric_std. They probably
will support other (almost) equivalent packages such as
std_logic_unsigned.

I think the (almost) equivalent package of numeric_std is the
std_logic_arith of synopsys, not std_logic_unsigned nor std_logic_signed.
The synopsys package std_logic_arith also declares the types signed and
unsigned (as is the case in numeric_std). One difference is the naming of
the function 'to_xxx' in numeric_std is equal to 'conv_xxx' in
std_logic_arith.

Egbert Molenkamp

 

[Jim Lewis]

For a quick tutorial on VHDL types and conversions see my
MAPLD paper, VHDL Math Tricks of the Trade. It is available
at http://www.synthworks.com/papers


Ben>>Is there a built in function that can convert a STD_LOGIC_VECTOR type
Ben>>to an 'unsigned' type?
Allan> No, there are no "built in" functions that do that.

Ironically the type casting you show is called implicit type conversion
and is built-in to the language.

To convert from an array to an integer requires a type conversion
function that is defined in one of the packages.

(BTW, std_logic_vector and unsigned aren't part of the the VHDL
language.)
What is VHDL? Is it IEEE 1076 or is it IEEE 1076 + the related

standards that were developed to support VHDL.

-- this won't work (arith isn't (and shouldn't be) defined for slv)
slv <= slv + 1;

This is a purist point of view.
If you include the package std_logic_unsigned it will work:
use ieee.std_logic_unsigned.all ; -- shareware from synopsys

This package overloads numeric operators allow std_logic_vector
to have an unsigned interpretation. Long term it is likely
that this package will be replaced by a similar package from
the IEEE 1076.3 working group.

There are three methodologies with respect to usage of the
std_logic_unsigned arithemetic package:
1) For math, only use types signed and unsigned from numeric_std
2) Permitted to use std_logic_unsigned for incrementers/counters
and testbenches. Use numeric_std for all other math.
3) Use std_logic_unsigned for any unsigned math.

Personally I use either 2 (preferred) or 1. 1 becomes
painful for some testbenches. In a testbench you often
need to do something like increment a std_logic_vector
typed address bus. Here the numerous type casting becomes
painful.

Recommendation: don't use the package std_logic_signed.
Like the other things, this is an opinion. While I am not
a purist, I also don't like chaos.


Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Ben Nguyen]

Thanks!

That worked great!

Ben

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<0urfmv0gj3ourln203h1f7pj1vet3or1v0@4ax.com>...

On 16 Sep 2003 20:07:04 -0700, benn686@hotmail.com (Ben Nguyen) wrote:

Is there a built in function that can convert a STD_LOGIC_VECTOR type
to an 'unsigned' type?

No, there are no "built in" functions that do that.
(BTW, std_logic_vector and unsigned aren't part of the the VHDL
language.)

but...

Yes, there are "standard" functions to do your conversion in the sense
that there are standard packages that add functionality you want to
the language: ieee.std_logic_1164 in the case of std_logic_vector, and
ieee.numeric_std in the case of unsigned and signed.

You will need to add the following lines to your VHDL source:

-- before your architecture
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

...

-- inside a declarative region in your architecture
signal un : unsigned(whatever downto 0);
signal slv : std_logic_vector(whatever downto 0);

...

-- now you can do conversions
un <= unsigned(slv);
slv <= std_logic_vector(un);

-- you can do arithmetic too
un <= un + 1;

-- this won't work (arith isn't (and shouldn't be) defined for slv)
slv <= slv + 1;


Note: some older tools don't support ieee.numeric_std. They probably
will support other (almost) equivalent packages such as
std_logic_unsigned.
Read the FAQ for details.

http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#integer_bit_vector

(Im using Xilinx's ISE 4.1 SP3)

6.1 SP1 is available.

Regards,
Allan.

 

[Niv]

-- this won't work (arith isn't (and shouldn't be) defined for slv)
slv <= slv + 1;

BUT, this will;

slv <= STD_LOGIC_VECTOR(UNSIGNED(slv) + 1);

assuming you use the ieee.numeric_std package.

I know, it's a bit unwieldly, but it sticks with pure ieee packages, no
Synopsys
ones.

Niv.