std_logic_vector to string function trouble

[Olaf Petzold]

Hi,

with the following piece of code:

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity slv2str is
end entity slv2str;

architecture behavior of slv2str is

function slv_to_str(vec : std_logic_vector) return string is
variable temp : string(vec'left+1 downto 1) := (others =>
'X');
begin
for i in vec'reverse_range loop
if (vec(i) = '1') then
temp(i+1) := '1';
elsif (vec(i) = '0') then
temp(i+1) := '0';
end if;
end loop;
return temp;
end function;

signal v : std_logic_vector(7 downto 0) := b"01001100";

begin

test : process is
variable l : line;
begin
write(l, slv_to_str(v(7 downto 6)) & slv_to_str(v(5 downto 0)));
writeline(output, l);
wait;
end process test;

end architecture behavior;

I get an unexpected result:

$ vcom.exe -93 slv2str.vhd
Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10
2004
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package textio
-- Compiling entity slv2str
-- Compiling architecture behavior of slv2str

$ vsim -c work.slv2str
Reading C:/Programme/mxe/tcl/vsim/pref.tcl

# 6.0a

# vsim -c work.slv2str
# Loading c:\programme\mxe\win32xoem/../std.standard
# Loading c:\programme\mxe\win32xoem/../ieee.std_logic_1164(body)
# Loading c:\programme\mxe\win32xoem/../std.textio(body)
# Loading ./work.slv2str(behavior)
VSIM 1> run 10 ns
# 01XXXXXX001100

I though that I will get a new copy of different size as the original
vector? Instead I get what? Is it bug or a language feature? How can I
solve it (without introducing temporaries of required length).

Thanks and Regards,
Olaf

 

[Ajeetha]

Hi,
Sorry for not having looked into your code in detail, quickly - why
not simply re-use Ben's IMAGE package for this? See:
http://members.aol.com/vhdlcohen/vhdl/vhdlcode/image_pb.vhd

HTH
Ajeetha
www.noveldv.com

 

[jens]

It appears as if the first call to the function is passing the
attributes (7 downto 6) and not (1 downto 0) as you were probably
hoping for, so slv_to_str(v(7 downto 6)) is actually returning
01XXXXXX.

Changing
variable temp : string(vec'left+1 downto 1) := (others => 'X');
to
variable temp : string(vec'left+1 downto vec'right+1) := (others =>
'X');
should hopefully work.

Separate the concatenation (i.e. print results on different lines) to
verify.

 

[Olaf Petzold]

It appears as if the first call to the function is passing the
attributes (7 downto 6) and not (1 downto 0) as you were probably
hoping for, so slv_to_str(v(7 downto 6)) is actually returning
01XXXXXX.

Changing
variable temp : string(vec'left+1 downto 1) := (others => 'X');
to
variable temp : string(vec'left+1 downto vec'right+1) := (others =
'X');
should hopefully work.

Separate the concatenation (i.e. print results on different lines) to
verify.

Thanks, this did the job.

Regards,
Olaf

 

[David Bishop]

Ajeetha wrote:

Hi,
Sorry for not having looked into your code in detail, quickly - why
not simply re-use Ben's IMAGE package for this? See:
http://members.aol.com/vhdlcohen/vhdl/vhdlcode/image_pb.vhd

You will find some very similar functions called "to_string" in the
additions to std.textio on:
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html