P
Piotr
Guest
Hi!
I'm beginner. I can't solve this problem. I'm trying to convert
std_logic_vector to integer.
It doesn't work. I have an error:
line 215: Different types for port <o> on entity and component for
<VectorToInteger>
------------
-- Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity VectorToInteger is port (
Clk_50MHz: in std_logic;
i: in std_logic_vector(7 downto 0);
o: out Integer range 300 downto -127);
end VectorToInteger;
architecture Behavioral of VectorToInteger is
begin
process(Clk_50MHz, i)
begin
if (rising_edge(Clk_50MHz)) then
o <= conv_integer(i);
end if;
end process;
end Behavioral;
-----------------
This is very important for me. Please help me...
Piotr
I'm beginner. I can't solve this problem. I'm trying to convert
std_logic_vector to integer.
It doesn't work. I have an error:
line 215: Different types for port <o> on entity and component for
<VectorToInteger>
------------
-- Code:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
entity VectorToInteger is port (
Clk_50MHz: in std_logic;
i: in std_logic_vector(7 downto 0);
o: out Integer range 300 downto -127);
end VectorToInteger;
architecture Behavioral of VectorToInteger is
begin
process(Clk_50MHz, i)
begin
if (rising_edge(Clk_50MHz)) then
o <= conv_integer(i);
end if;
end process;
end Behavioral;
-----------------
This is very important for me. Please help me...
Piotr